A Digital Deformation Vacuum Gauge with an LC-Generator

The design of a sylphon bellows sensor and the basic circuits of an LC-generator and of a microprocessor unit are presented. An analytical pressure–frequency conversion function and a special method of adjusting the sensor ensure an error of less than 0.05%. The dynamic range is up to 10⁵. The instruments developed cover the ranges 10³, 10⁴, and 10⁵ Pa.     

Work of fracture of high impact polystyrene (HIPS) film under plane stress conditions

Essential work of fracture methodology was used to determine plane-stress ductile fracture toughness of high impact polystyrene film of thickness 0.26 mm. Results obtained indicated that specific essential work of fracture, w _e, is independent of loading rate, and for certain specimen sizes, independent of both gauge length and width of the specimen. On the other hand, w _e was found to be affected by the temperature, molecular anisotropy and the geometry of the test specimens. Reasonable estimate of w _e was obtained via crack opening displacement value.     

Robust vector control of induction motors using full-order observer in consideration of core loss

This paper proposes a method for designing a robust full-order observer for vector-controlled induction motors taking core loss into account. Although conventional research focuses on parameter identification, global stability of the identification remains questionable. Therefore, robustness against some parameters is required. This paper describes the design of a robust full-order observer which takes core loss into account, using both the gain-scheduled H/sub /spl infin// control and the linear matrix inequality technique. This design always results in a stable controller. The robustness of the proposed method against variations of resistances is evaluated by experiments.     

Assessing stem cell research productivity

Honour Index (HoI), a method to evaluate research performance within different research fields, was derived from the impact factor (IF). It can be used to rate and compare different categories of journals. HoI was used in this study to determine the scientific productivity of stem cell research in the Asian Four Dragons (Hong Kong, Singapore, South Korea and Taiwan) from 1981 to 2001. The methodology applied in this study represents a synthesis of universal indicator studies and bibliometric analyses of subfields at the micro-level. We discuss several comparisons, and conclude the developmental trend in stem cell research for two decades. This revised version was published online in August 2006 with corrections to the Cover Date.     

Electrochemical synthesis and characterization of chloride doped polyaniline

Chloride doped polyaniline conducting polymer films have been prepared in a protic acid medium (HCl) by potentiodynamic method in an electrochemical cell and studied by cyclic voltammetry and FTIR techniques. The FTIR spectra confirmed Cl^- ion doping in the polymers. The polymerization rate was found to increase with increasing concentration of aniline monomer. But the films obtained at high monomer concentration were rough having a nonuniform flaky polyaniline distribution. Results showed that the polymerization rate did not increase beyond a critical HCl concentration. Cyclic voltammetry suggested that, the oxidation-reduction current increased with an increase in scan rate and that the undoped polyaniline films were not hygroscopic whereas chloride doped polyaniline films were found to be highly hygroscopic.     

A redundant multivalued logic for a 10-Gb/s CMOS demultiplexer IC

A redundant multivalued logic is proposed for high-speed communication ICs. In this logic, serial binary data are received and converted into parallel redundant multivalued data. Then they are restored into parallel binary data. Because of the multivalued data conversion, this logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was fabricated using a 0.18-/spl mu/m CMOS process. The IC achieved an operating speed of 10 Gb/s with a supply voltage of only 1.3 V and with power consumption of 38 mW. This logic may achieve CMOS communication ICs with an operating speed several times greater than 10 Gb/s.     

Reducing CIC filter complexity

This paper provides several tricks to reduce the complexity and enhance the usefulness of cascaded integrator-comb (CIC) filters. The first trick shows a way to reduce the number of adders and delay elements in a multi-stage CIC interpolation filter. The result is a multiplierless scheme that performs high-order linear interpolation using CIC filters. The second trick shows a way to eliminate the integrators from CIC decimation filters. The benefit is the elimination of unpleasant data word growth problems.     

A New Hand-Held Microsystem Architecture for Biological Analysis

This paper presents a hand-held microsystem based on new fully integrated magnetoresistive biochips for biomolecular recognition (DNA hybridization, antibody antigen interaction, etc.). Magnetoresistive chip surfaces are chemically treated, enabling the immobilization of probe biomolecules such as DNA or antibodies. Fluid handling is also integrated in the biochip. The proposed microsystem not only integrates the biochip, which is an array of 16times16 magnetoresistive sensors, but it also provides all the electronic circuitry for addressing and reading out each transducer. The proposed architecture and circuits were specifically designed for achieving a compact, programmable and portable microsystem. The microsystem also integrates a hand-held analyzer connected through a wireless channel. A prototype of the system was already developed and detection of magnetic nanoparticles was obtained. This indicates that the system may be used for magnetic label based bioassays     

A power-driven multiplication instruction-set design method for ASIPs

This paper presents a novel power-driven multiplication instruction-set design method for application-specific instruction-set processors (ASIPs). Based on a dual-and-configurable-multiplier structure, our proposed method devises a multiplication instruction set for low-power ASIPs. Our method exploits the execution sequences of multiplication instructions and effective bit widths of variables to reduce power consumed by redundant multiplication bits while minimizing the multiplication execution time. Experimental results on a set of DSP programs demonstrate that our proposed method achieves significant power reduction (up to 18.53%) and execution time improvement (up to 10.43%) with 18% area overhead.