Influence of device engineering on the analog and RF performances of SOI MOSFETs

This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS).     

High-gain hybrid amplifier consisting of cascaded fluoride-based TDFA and silica-based EDFA in 1458-1540 nm wavelength region

A hybrid optical fibre amplifier is described that consists of a fluoride-based thulium-doped fibre amplifier and a silica-based erbium-doped fibre amplifier connected in a cascade. The amplifier has a gain of more than 25 dB and a noise figure of less than 9 dB over a wide wavelength region of 1458-1540 nm.     

Static energy reduction techniques for microprocessor caches

Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques.     

High-performance MIM capacitor using ALD high-k HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectrics

For the first time, we successfully fabricated and demonstrated high performance metal-insulator-metal (MIM) capacitors with HfO/sub 2/-Al/sub 2/O/sub 3/ laminate dielectric using atomic layer deposition (ALD) technique. Our data indicates that the laminate MIM capacitor can provide high capacitance density of 12.8 fF//spl mu/m/sup 2/ from 10 kHz up to 20 GHz, very low leakage current of 3.2 /spl times/ 10/sup -8/ A/cm/sup 2/ at 3.3 V, small linear voltage coefficient of capacitance of 240 ppm/V together with quadratic one of 1830 ppm/V/sup 2/, temperature coefficient of capacitance of 182 ppm//spl deg/C, and high breakdown field of /spl sim/6 MV/cm as well as promising reliability. As a result, the HfO/sub 2/-Al/sub 2/O/sub 3/ laminate is a very promising candidate for next generation MIM capacitor for radio frequency and mixed signal integrated circuit applications.     

Low-temperature poly-SiGe alloy growth of high gain/speed pin infrared photosensor with gold-induced lateral crystallization (Au-ILC)

The hydrogenated poly-silicon germanium (poly-SiGe:H) epitaxial film has been investigated using gold-induced lateral crystallization (Au-ILC) technology on a-SiGe:H layers at 10-h 350/spl deg/C annealing temperature and 60-sccm hydrogen (H/sub 2/) content. Using this optimal condition, the growth rate of the induced Au was as large as 15.9 /spl mu/m/h. With a low annealing temperature (/spl les/400/spl deg/C) and large growth rate, this novel technology will be noticeably useful for poly-SiGe:H pin IR-sensing fabrication on a conventional precoated indium tin oxide (ITO)-glass substrate. Under a 1-/spl mu/W IR-LED incident light (with peak wave length at 710 nm) and at a 5-V biased voltage, the poly-SiGe:H pin IR sensor developed by the Au-ILC technology, i.e., an Al (anode)/n poly-SiGe:H/i poly-SiGe:H/p poly-SiGe:H/ITO (cathode)/glass-substrate structure allowed for maximum optical gain and response speed. The optical gains and the response speeds were almost 600 and 130%, respectively, better than that of a traditional pin type. Meanwhile, the FWHM of a poly-SiGe:H pin sensor with Au-ILC technology was reduced from 280 to 150 nm. This reveals excellent IR-sensing selectivity. These IR-sensing trials demonstrated again that the proposed Au-ILC technology has very useful application in the field of low cost integrated circuits on optoelectronic applications.     

Hydrogen annealing effect on DC and low-frequency noise characteristics in CMOS FinFETs

The hydrogen annealing process has been used to improve surface roughness of the Si-fin in CMOS FinFETs for the first time. Hydrogen annealing was performed after Si-fin etch and before gate oxidation. As a result, increased saturation current with a lowered threshold voltage and a decreased low-frequency noise level over the entire range of drain current have been attained. The low-frequency noise characteristics indicate that the oxide trap density is reduced by a factor of 3 due to annealing. These results suggest that hydrogen annealing is very effective for improving device performance and for attaining a high-quality surface of the etched Si-fin.     

用于单芯片系统的改进型WXGA LCoS成像器

本文讨论用于单芯片时序混色的菲利浦DD-720硅基液晶(LCoS)片。这种芯片主要用于HDTV背投影机和多媒体系统。与菲利浦以前的单片LCoS设计相比，由于该芯片具有电接口接点较少、封装简单和温度传感器内置等许多特点，使其应用于投影系统时成本降低。     

The effects of nonlocal impact ionization on the speed of avalanche photodiodes

The nonlocal enhancement in the velocities of charge carriers to ionization is shown to outweigh the opposing effects of dead space, increasing the avalanche speed of short avalanche photodiodes (APDs) over the predictions of a conventional local model which ignores both of these effects. The trends in the measured gain-bandwidth product of two short InAlAs APDs reported in the literature support this result. Relatively large speed benefits are predicted to result from further small reductions in the lengths of short multiplication regions.     

Simulating strength and failure in engineering plant

Current features are considered in the calculation of carrying capacities for constructions in engineering plant (EP). Methods and algorithms are described for EP calculations with comprehensive incorporation of the effects from technological and working defects on the behavior of structures under standard and emergency conditions. __________ Translated from Khimicheskoe i Neftegazovoe Mashinostroenie, No. 8, pp. 38–40, August, 2006.