Analysis of issues in gate recess etching in the InAlAs/InGaAs HEMT manufacturing process

We have developed an InAlAs/InGaAs metamorphic high electron mobility transistor device fabrication process where the gate length can be tuned within the range of 0.13 μm–0.16 μm to suit the intended application. The core processes are a two-step electron-beam lithography process using a three-layer resist and gate recess etching process using citric acid. An electron-beam lithography process was developed to fabricate a T-shaped gate electrode with a fine gate foot and a relatively large gate head. This was realized through the use of three-layered resist and two-step electron beam exposure and development. Citric acid-based gate recess etching is a wet etching, so it is very important to secure etching uniformity and process reproducibility. The device layout was designed by considering the electrochemical reaction involved in recess etching, and a reproducible gate recess etching process was developed by finding optimized etching conditions. Using the developed gate electrode process technology, we were able to successfully manufacture various monolithic microwave integrated circuits, including low noise amplifiers that can be used in the 28 GHz to 94 GHz frequency range.     

Creep behavior of the ternary 95.5Sn-3.9Ag-0.6Cu solder—Part I: As-cast condition

The compression creep behavior was studied for the ternary solder alloy 95.5Sn-3.9Ag-0.6Cu in the as-cast condition. Samples were tested under stresses of 2–45 MPa and temperatures of −25–160°C. There was a significant variability in the creep curve shape, strain magnitude, and steady-state strain-rate properties. A multivariable linear-regression analysis of the steady-state strain-rate data, using the sinh-law stress representation, indicated two mechanisms distinguished by low- and high-temperature regimes of −25–75°C and 75–160°C, respectively. The sinh-law stress exponent (n) and apparent-activation energy (ΔH) in the −25–75°C regime were 4.4 ± 0.7 kJ/mol and 25 ± 7 kJ/mol (63% confidence intervals), respectively. Those same parameters in the 75–160°C regime were 5.2±0.8 kJ/mol and 95±14 kJ/mol, respectively, for the high-temperature regime. The values of ΔH suggested a short-circuit diffusion mechanism at low temperatures and a lattice or bulk-diffusion mechanism at high temperatures. The stress dependency of the steady-state strain rate did not indicate a strong power-law breakdown behavior or a threshold stress phenomenon. Cracks and grain-boundary sliding were not observed in any of the samples. As the creep temperature increased, a coarsened particle boundary and particle depletion zone formed in the region of fine Ag₃Sn particles that existed between the Sn-rich phase areas. The coarsened particle boundary, as well as accelerated coarsening of Ag₃Sn particles, were direct consequences of the creep deformation process.     

Improved Scalar Multiplication on Elliptic Curves Defined over F2mn

We propose two improved scalar multiplication methods on elliptic curves over F_qn where q = 2^m using Frobenius expansion. The scalar multiplication of elliptic curves defined over subfield F_q can be sped up by Frobenius expansion. Previous methods are restricted to the case of a small m. However, when m is small, it is hard to find curves having good cryptographic properties. Our methods are suitable for curves defined over medium‐sized fields, that is, 10 ≤ m ≤ 20. These methods are variants of the conventional multiple‐base binary (MBB) method combined with the window method. One of our methods is for a polynomial basis representation with software implementation, and the other is for a normal basis representation with hardware implementation. Our software experiment shows that it is about 10% faster than the MBB method, which also uses Frobenius expansion, and about 20% faster than the Montgomery method, which is the fastest general method in polynomial basis implementation.     

Exhaustive Output Arbitration of Input Buffered Switch with Buffered Crossbar

We propose a new arbitration method for an input buffered switch with a buffered crossbar. In the proposed method, an exhaustive polling method is used to decrease the synchronization. Using an approximate analysis, we explain how the proposed method improves the switch performance. Also, using computer simulations, we show the proposed method outperforms the previous methods under burst traffic.     

New two CFOA-based sinusoidal RC oscillators with buffered outlet

Using a unified representation for a class of buffered-outlet two current-feedback operational amplifier (CFOAs)-based sinusoidal oscillators, new circuits of this type can be systematically discovered. A catalogue of four circuit structures, each structure realizing nine oscillator circuits, is presented. Moreover, using the RC:CR transformation, additional nine oscillator circuits can be obtained from each structure. While each circuit requires five passive elements, some of the circuits enjoy one or more of the following attractive features: use of grounded capacitors, feasibility of absorbing the parasitic components of the CFOAs and orthogonal tuning of the frequency and the startup condition of oscillation.     

Collaborative and Cognitive Network Platforms: Vision and Research Challenges

In this paper, we present a visionary concept referred to as Collaborative and Cognitive Network Platforms (CCNPs) as a future-proof solution for creating a dependable, self-organizing and self-managing communication substrate for effective ICT solutions to societal problems. CCNP creates a cooperative communication platform to support critical services across a range of business sectors. CCNP is based on the personal network (PN) technology which is an inherently cooperative environment prototyped in the Dutch Freeband PNP2008 and the European Union IST MAGNET projects. In CCNP, the cognitive control plane strives to exploit the resources to better satisfy the requirements of networked applications. CCNP facilitates collaboration inherently. Through cognition in the cognitive control plane, CCNP becomes a self-managed substrate. The self-managed substrate, in this paper, is defined as cognitive and collaborative middleware on which future applications run without user intervention. Endemic sensor networks may be incorporated into the CCNP concept to feed its cognitive control plane. In this paper, we present the CCNP concept and discuss the research challenges related to collaboration and cognition.     

Accelerating Machine-Learning Algorithms on FPGAs using Pattern-Based Decomposition

Machine-learning algorithms are employed in a wide variety of applications to extract useful information from data sets, and many are known to suffer from super-linear increases in computational time with increasing data size and number of signals being processed (data dimension). Certain principal machine-learning algorithms are commonly found embedded in larger detection, estimation, or classification operations. Three such principal algorithms are the Parzen window-based, non-parametric estimation of Probability Density Functions (PDFs), K-means clustering and correlation. Because they form an integral part of numerous machine-learning applications, fast and efficient execution of these algorithms is extremely desirable. FPGA-based reconfigurable computing (RC) has been successfully used to accelerate computationally intensive problems in a wide variety of scientific domains to achieve speedup over traditional software implementations. However, this potential benefit is quite often not fully realized because creating efficient FPGA designs is generally carried out in a laborious, case-specific manner requiring a great amount of redundant time and effort. In this paper, an approach using pattern-based decomposition for algorithm acceleration on FPGAs is proposed that offers significant increases in productivity via design reusability. Using this approach, we design, analyze, and implement a multi-dimensional PDF estimation algorithm using Gaussian kernels on FPGAs. First, the algorithm’s amenability to a hardware paradigm and expected speedups are predicted. After implementation, actual speedup and performance metrics are compared to the predictions, showing speedup on the order of 20× over a 3.2 GHz processor. Multi-core architectures are developed to further improve performance by scaling the design. Portability of the hardware design across multiple FPGA platforms is also analyzed. After implementing the PDF algorithm, the value of pattern-based decomposition to support reuse is demonstrated by rapid development of the K-means and correlation algorithms.     

Holography and plasma oxidation for uniform nanoscale two dimensional channel formation of vertical organic field-effect transistors with suppressed gate leakage current

Vertical organic field-effect transistors (VOFETs) with nanoscale channel openings have been fabricated using pentacene as an active layer material. To achieve uniform nanoscale two-dimensional channel openings, a laser holography lithography has been introduced. Uniformly distributed and well-aligned holes with 250 nm diameter were successfully obtained with the laser holography lithography. VOFET devices with these channel openings have shown high on/off ratio of about 10³ without any further treatment. Gate leakage current was also decreased with an additional insulating layer generated on the gate electrode sidewall via plasma oxidation.     

Hot embossing of diffractive optically variable images in biaxially-oriented polypropylene

The hot embossing of grating-based optically variable devices has been demonstrated in biaxially-oriented polypropylene (BOPP). Embossing of the grating structures was examined over a range of temperatures (80-155 °C) at 135 kN force. However, only at temperatures above the glass transition temperature, T_g, was high quality replication achieved over a full embossing area of 80 × 80 mm. The embossing of several different types of optically variable device has been examined including portrait, non-portrait and 3-dimensional images. The images embossed into BOPP have displayed an optically variable effect when viewed in transmitted light.     

Scalable Gaussian Normal Basis Multipliers over GF(2<Superscript><Emphasis Type=Italic>m</Emphasis></Superscript>) Using Hankel Matrix-Vector Representation

This work presents a novel scalable multiplication algorithm for a type-t Gaussian normal basis (GNB) of GF(2^m). Utilizing the basic characteristics of MSD-first and LSD-first schemes with d-bit digit size, the GNB multiplication can be decomposed into n(n + 1) Hankel matrix-vector multiplications. where n = (mt + 1)/d. The proposed scalable architectures for computing GNB multiplication comprise of one d × d Hankel multiplier, four registers and one final reduction polynomial circuit. Using the relationship of the basis conversion from the GNB to the normal basis, we also present the modified scalable multiplier which requires only nk Hankel multiplications, where k = mt/2d if m is even or k = (mt − t + 2)/2d if m is odd. The developed scalable multipliers have the feature of scalability. It is shown that, as the selected digit size d ≥ 8, the proposed scalable architectures have significantly lower time-area complexity than existing digit-serial multipliers. Moreover, the proposed architectures have the features of regularity, modularity, and local interconnection ability. Accordingly, they are well suited for VLSI implementation.