基于白化权函数聚类法的航电系统效能评估

航空电子综合系统是作战飞机的神经中枢,准确评估航电系统的效能对我国航空电子技术的发展具有重要意义。为了用灰色白化权函数聚类法对基于1553B总线的航电系统进行效能评估。首先将1553B总线负载、延迟时间、总线使用效率三项指标分为优、良、中、差四个灰类,综合各指标的白化权函数和其隶属于不同灰类的权重得到航电系统聚类系数向量,然后由该向量中的最大聚类系数所属灰类来确定该航电系统的灰类等级。灰色白化权函数聚类方法为航电系统的设计和效能评估提供了重要方法和理论依据。     

HH神经元的自抗扰同步研究

因外部电磁环境变化导致生物神经元放电节律不同步是生物控制中需要解决的一个难点问题。HH神经元模型是描述神经元动力学特性的第一个数学模型,以HH神经元为研究对象,利用各种现代控制方法获得HH神经元的同步,方法的不足在于对外部干扰的敏感性以及控制律复杂不易实现。为增强神经元同步的鲁棒性和可行性,利用自抗扰控制算法,在三种不同情况下研究HH神经元的同步,并且依次加入不同干扰验证其同步效果。仿真结果表明,自抗扰控制能够对神经元系统的总扰动进行实时估计和补偿,消除扰动对神经元系统同步的影响,从而获得良好的同步效果。     

计算机网络的信息安全与防护策略探究

伴随着我国高度的信息化和网络化,互联网得到了大量的普及,虽然它给我们的生活带来的极大的方便,但也有一些不法行为肆意的破坏着网络的系统,给用户带来的诸多的不便。本文针对计算机网络的信息安全与防护进行深入的探讨。     

提高计算机软件课程教学效果的思考

在信息技术时代的今天,伴随着计算机技术的迅猛发展以及在日常生活和工作中的普及,我们如何掌握常用的计算机应用软件成为每个人工作学习中不可缺少的课程。在该课程的教学过程中,教师应选择合适的版本,以培养学生的动手能力、自学能力和创新意识为出发点,综合运用实例教学法、任务驱动教学法等方法,同时给学生创造一个自主的学习环境,并建立灵活的评价体系,以增强教学效果。     

基于ADSP21060的并行信号处理系统设计

实时识别目标在现代高科技战争中具有重要军事意义。设计了一个由5片ADSP21060组成的并行处理系统。该系统采用基于环网的数据块处理策略,主DSP将数据分割为长度相等的块,并分配给各从DSP进行处理。以FIR滤波器并行算法为例,验证了本设计在运算速度方面显著优于单DSP系统。该设计可应用到对实时性能要求苛刻的军事领域。     

Effect of test method and crack size on the fracture toughness of a chain-silicate glass-ceramic

The fracture toughness of a canasite glass-ceramic with a highly acicular, interlocked grain structure was measured by a number of different methods. The values at room temperature obtained by the chevron-notch, short-bar and notched-beam methods ranged from 4 to 5 M Pa m^–1/2, well above literature values for other glass-ceramics. Similar values of toughness were obtained by the fracture of bars with indentation cracks introduced with loads ranging from 1.96 to 400 N, but only for crack sizes >200 m, with lower values for cracks of smaller size. The toughness values obtained by the direct measurement of the size of the indentation cracks were appreciably lower than the values obtained by all other methods over the total range of indentation loads and corresponding crack size. SEM fractography showed that the surface within the indentation cracks was appreciably smoother than the surrounding fracture surface. The high values of fracture toughness were attributed to the combined mechanisms of crack-deflection and microcrack-toughening due to the stress-enhanced creation of microcracks caused by the residual stresses which arise from the thermal expansion anisotropy of the canasite monoclonic crystal structure. The strong negative temperature dependence of the fracture toughness suggests that at room temperature microcrack toughening represents the primary contributing mechanism to the fracture toughness. The combined effects of crack-deflection and microcrack-toughening can lead to the development of glass-ceramics with greatly improved resistance to crack propagation.     

Effects of junction formation conditions on the photovoltaic properties of sintered CdS/CdTe solar cells

Microstructures and properties of sintered CdS films on glass substrates and sintered CdTe films on polycrystal CdS substrates have been investigated. The CdS films, which contained 9 wt % CdCl₂ as a sintering aid and were sintered at 650° C for 1 h in nitrogen, are transparent and have an average grain size of 15m and an electrical resistivity of 0.5cm. The CdTe films, which were coated on the sintered CdS substrate and were sintered above 610° C for 1 h in nitrogen, have a dense structure with an average grain size larger than 5m. All polycrystal CdS/CdTe solar cells were fabricated by this successive coating and sintering method. The sintering temperature of CdTe films on the sintered CdS films was varied from 585 to 700° C. Compositional interfaces and p-n juctions are formed during sintering. The highest solar efficiency (7.18%) was found in a solar cell made by sintering the composite layer of glass-CdS-CdTe at 625° C for 1 h. A fabrication temperature below 610° C resulted in poor solar cell efficiencies due to the porous structure of the CdTe films and above 650° C also resulted in poor efficiencies due to the formation of a CdS_1-x Te_x layer at the interface and a large p-n junction depth.     

A built-in test pattern generator

Built-in testing is currently of more concern due to the difficulties in testing a VLSI byusing an external tester.In addition,Built-In Testing is also necessary for on-line testing and afault-tolerant computing system.Using a Linear Feedback Shift Register(LFSR)as a built-intest pattern generator(BITPG)is a realistic and simple approach.An LFSR with maximumlength can generate pseudo-random test patterns or all non-null vectors for exhaustive testing.This paper presents an LFSR design with non-maximum length to serve as a BITPG to generatea given test set T,which efficiently saves testing time.A search-verification process fordesigning this kind of LFSR is employed and implemented by the program SVBITPG.Thispaper presents the diagram of tire program and gives stone examples to illustrate the design ofthe BITPG.