High Performance β-Ga2O3 Schottky Barrier Transistors with Large Work Function TMD Gate of NbS2 and TaS2

Gallium trioxide, β-Ga₂O₃, has been recently studied due to its promising semiconducting properties as active material in transistors or Schottky diodes. Transistors with β-Ga₂O₃ channels are mostly metal oxide field effect transistors (MOSFET), and they show very negative threshold voltages (V_th) in general. Metal semiconductor field effect transistors (MESFETs) with top gate are also reported with less negative V_th. Still, β-Ga₂O₃ MESFETs are only a few. Here, bottom gate architecture β-Ga₂O₃ MESFETs using transition metal dichalcogenide (TMD) NbS₂ and TaS₂ are reported. Due to the large work functions of those metallic TMDs, the MESFETs display minimum subthreshold swing of 61 mV dec⁻¹, small V_th of −1.2 V, minimum OFF I_D of ≈100 fA, and maximum ON/OFF current ratio of ≈10⁸. Both β-Ga₂O₃ Schottky diodes with TaS₂ and NbS₂ display good junction stability even after 300 °C measurements in 10 mTorr vacuum. When the β-Ga₂O₃ MESFET with TaS₂ gate is integrated as a switching FET into an organic light emitting diode (OLED) circuit, it demonstrates long-term leakage endurance performance, maintaining an OLED brightness higher than 58% of the initial intensity after 100 s passes since the ON-switching point, which is even superior to the performance of conventional a-IGZO MOSFET switch.     

Well‐Defined Functional Linear Aliphatic Diblock Copolyethers: A Versatile Linear Aliphatic Polyether Platform for Selective Functionalizations and Various Nanostructures

Low‐temperature anionic ring‐opening homopolymerizations and copolymerizations of two glycidol derivatives (allyl glycidyl ether (AGE) and ethoxyethyl glycidyl ether (EEGE)) are studied using a metal‐free catalyst system, 3‐phenyl‐1‐propanol (PPA) (an initiator) and 1‐tert‐butyl‐4,4,4‐tris(dimethylamino)‐2,2‐bis[tris‐(dimethylamino)phosphoranylidenamino]‐2Λ⁵,4Λ⁵‐catenadi(phosphazene) (t‐Bu‐P₄) (a promoter) in order to obtain well‐defined functional linear polyethers and diblock copolymers. With the aid of the catalyst system, AGE is found to successfully undergo anionic ring‐opening polymerization (ROP) even at room temperature (low reaction temperature) without any side reactions, producing well‐defined linear AGE‐homopolymer in a unimodal narrow molecular weight distribution. Under the same conditions, EEGE also undergoes polymerization, producing a linear EEGE‐homopolymer in a unimodal narrow molecular‐weight distribution. In this case, however, a side reaction (i.e., chain‐transfer reaction) is found to occur at low levels during the early stages of polymerization. The chemical properties of the monomers in the context of the homopolymerization reactions are considered in the design of a protocol used to synthesize well‐defined linear diblock copolyethers with a variety of compositions. The approach, anionic polymerization via the sequential step feed of AGE and EEGE as the first and second monomers, is found to be free from side reactions at room temperature. Each block of the obtained linear diblock copolymers undergoes selective deprotection to permit further chemical modification for selective functionalization. In addition, thermal properties and structures of the polymers and their post‐modification products are examined. Overall, this study demonstrates that a low‐temperature metal‐free anionic ROP using the PPA/t‐Bu‐P₄ catalyst system is suitable for the production of well‐defined linear AGE‐homopolymers and their diblock copolymers with the EEGE monomer, which are versatile and selectively functionalizable linear aliphatic polyether platforms for a variety of post‐modifications, nanostructures, and their applications.     

CdSe-sensitized inorganic–organic heterojunction solar cells: The effect of molecular dipole interface modification and surface passivation

CdSe-sensitized heterojunction solar cells composed of mesoscopic TiO₂/CdSe/P3HT (poly-3-hexylthiophene) were constructed, and the negative molecular dipole of 4-methoxybenzenethiol (MBT) and the ZnS passivation layer were used as interface modifiers to improve device performance. Through the interface modification between TiO₂/CdSe and P3HT using MBT and by ZnS surface passivation, the power conversion efficiency of the modified solar cell was greatly enhanced from 1.02% to 1.62% under 1 sun illumination.     

Simple and Accurate Design of Low-Density Parity-Check Codes for Multi-Input Multi-Output Systems

In this paper we design an irregular low-density parity-check (LDPC) code for multiple-input multiple-output (MIMO) systems, using a simple extrinsic information transfer (EXIT) chart method. The MIMO systems considered are the optimal maximum a posteriori probability (MAP) detector and the suboptimal minimum mean square error soft-interference cancellation (MMSE-SIC) detector. The MIMO detector and the LDPC decoder exchange soft information and form a turbo iterative receiver. The EXIT charts are used to obtain the edge degree distribution of the irregular LDPC code which is optimized for the MIMO detector. It is shown that the performance of the designed LDPC code is better than that of conventional LDPC code which was optimized for either the Additive White Gaussian Noise (AWGN) channel or the MIMO channel without an explicit consideration of the given detector structure.     

A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

A Multi‐Strategic Concept‐Spotting Approach for Robust Understanding of Spoken Korean

We propose a multi‐strategic concept‐spotting approach for robust spoken language understanding of conversational Korean in a hostile recognition environment such as in‐car navigation and telebanking services. Our concept‐spotting method adopts a partial semantic understanding strategy within a given specific domain since the method tries to directly extract pre‐defined meaning representation slot values from spoken language inputs. In spite of partial understanding, we can efficiently acquire the necessary information to compose interesting applications because the meaning representation slots are properly designed for specific domain‐oriented understanding tasks. We also propose a multi‐strategic method based on this concept‐spotting approach such as a voting method. We present experiments conducted to verify the feasibility of these methods using a variety of spoken Korean data.     

Shorted Microstrip Patch Antenna Using Inductively Coupled Feed for UHF RFID Tag

A very small patch‐type RFID tag antenna (UHF band) using ceramic material mountable on metallic surfaces is presented. The size of the proposed tag is 25 mm×25 mm×3 mm. The impedance of the antenna can be easily matched to the tag chip impedance by adjusting the size of the shorting plate of the patch and the size of the feeding loop. The measured maximum reading distance of the tag at 910 MHz was 5 m when it was mounted on a 400 mm × 400 mm metallic surface. The proposed design is verified by simulation and measurements which show good agreement.     

Writing current reduction and total set resistance analysis in PRAM

We evaluated the limit of scaling bottom electrode contact (BEC) heater size and high resistivity heater to reduce writing current. It was found that the resistivity of heater should be increased for reducing writing current below the heater size of about 50 nm without any undesirable increase of resistance of the crystalline state (SET state, Rset). It was shown in the numerical simulations that the dissipated heat loss through BEC during melting GST was decreased in the increase of resistivity of heater. In addition, we analyzed the resistance components contributing to the total set resistance. It was observed that the undesired sharp increase of Rset as the BEC size decreases below 50 nm was attributed to the resistance component of GST–BEC interface. In the case of high resistivity heater, the contributions of both incomplete crystallization and heater itself were enhanced.     

Stress Mechanism about Field Lightning Surge of High Voltage BJT Based Line Driver for ADSL System

In this paper, we have verified stress root caused by lightning surge in High voltage BJT based line driver of ADSL telecommunication and created failure mechanism. To reproduce damages in Line driver, we have applied STD surge waveform in operating condition, which is specified in IEC-6000-4-5, to component and board level. Visual isolation for Damage root was conducted with Real-time Electrical Stress Analysis (RTESA) utilizing Photon Emission Microscopy (PEM). The surge made with input of Tx output created junction breakdown of amplifier, which is made of HVBJT cells, and also caused current crowding from Vcc (supply voltage). In case of Positive pulse, current crowding was observed from between Collector and Vcc (+)12V. For negative pulse, at between Emitter and Vee (−)12V, current crowding was found. For both cases, device damage level was the same. All of these could be considered as transient latchup phenomenon created in BJT cell. Applying temporary clamping diode to line driver Tx, we have conducted Board level surge injection test. As a result, with the correlation between surge level from component level reproduction test and the one from system level, we have decided field lightning surge damage level and set up line driver protection margin.     

A new method to suppress harmonics using /spl lambda//4 bias line combined by defected ground structure in power amplifiers

A new /spl lambda//4 bias line combined by a dumb-bell shaped defected ground structure (DGS) is proposed to suppress harmonics in power amplifiers. The proposed DGS bias line maintains the required high impedance even after DGS is inserted, while the width and length of the /spl lambda//4 bias line are broader and shorter than those of conventional bias lines. When the DGS bias line is used in power amplifiers, the third harmonic components as well as the second harmonic are reduced, because of the increased slow-wave effect over wide harmonic band. It is shown that the reduction of the third harmonic component, the improvement of 1 dB compression point, and power added efficiency are 26.5 dB, 0.45 dB, and 9.1%, respectively.