FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm

This paper presents a high throughput digital design of the 128-bit Advanced Encryption Standard (AES) algorithm based on the 2-slow retiming technique on FPGA. The C-slow retiming is a well-known optimization and high performance technique. It can enhance designs with feedback loops and automatically rebalances the registers in the design. The C-slow retiming can break the critical path of the design into finer pieces to improve the throughput of the design. The complexity of the C-slow retiming on FPGA is to find the best register allocation in the data path of the design so that by increasing the number of registers, relocation of the registers to balance the AES architecture be in the best mode, and the critical path be optimally pipelined and improved. In this paper, architecture of the AES algorithm is implemented in the gate level by high-speed and breakable structures that are desirable for the 2-slow retiming. The Mix-columns transformation is implemented based on multiplication by constants 2 and 3 modules with combinational logic circuits. This work has been successfully verified and synthesized using Xilinx ISE 11 byVirtex-5, XC5VLX85 FPGA. The proposed implementation achieves a high throughput of 86 Gb/s and high maximum operation frequency of 671.524 MHz whereas the highest throughput and the highest operation frequency reported in the literature are 73.737 Gb/s and 576.07 MHz, respectively.     

Optimized SVD-based robust watermarking in the fractional Fourier domain

Digital watermarking is one of the most effective methods for protecting multimedia from different kind of threats. It has been used for many purposes, like copyright protection, ownership identification, tamper detection, etc. Many watermarking applications require embedding techniques that provide robustness against common watermarking attacks, like compression, noise, filtering, etc. In this paper, an optimized robust watermarking method is proposed using Fractional Fourier Transform and Singular Value Decomposition. The approach provides a secure way for watermarking through the embedding parameters that are required for the watermark extraction. It is a block-based method, where each watermark bit is embedded in its corresponding image block. First, the transform is applied to each block, and then the singular values are evaluated through which the embedding modification is performed. The optimum fractional powers, of the transform, and the embedding strength factor are evaluated through a Meta-heuristic optimization to optimize the watermark imperceptibility and robustness. The Artificial Bee Colony is used as the Meta-heuristic optimization method. A fitness function is employed, at the optimization process, through which the maximum achievable robustness can be provided without degrading the watermarking quality below a predetermined quality threshold Qth. The effectiveness of the proposed method is demonstrated through a comparison with recent watermarking techniques in terms of the watermarking performance. The watermarking quality and robustness are evaluated for different quality threshold values. Experimental results show that the proposed approach achieves a better quality compared to that of other existing watermarking methods. On the other hand, the robustness is examined against the most common applied attacks. It is noticed that the proposed method can achieve a higher robustness degree when decreasing the quality threshold value.     

Energy efficient and robust allocation of interdependent tasks on mobile ad hoc computational grid

A mobile ad hoc computational grid is a distributed computing infrastructure that allows mobile nodes to share computing resources in a mobile ad hoc environment. Compared to traditional distributed systems such as grids and clouds, resource allocation in mobile ad hoc computational grids is not straightforward because of node mobility, limited battery power and an infrastructure‐less network environment. The existing schemes are either based on a decentralized architecture that results in poor allocation decisions or assume independent tasks. This paper presents a scheme that allocates interdependent tasks and aims to reduce task completion time and the amount of energy consumed in transmission of data. This scheme comprises two key algorithms: resource selection and resource allocation. The resource selection algorithm is designed to select nodes that remain connected for a longer period, whereas the resource assignment or allocation algorithm is developed to allocate interdependent tasks to the nodes that are accessible at the minimum transmission power. The scheme is based on a hybrid architecture that results in effective allocation decisions, reduces the communication cost associated with the exchange of control information, and distributes the processing burden among the nodes. The paper also investigates the relationship between the data transfer time and transmission energy consumption and presents a power‐based routing protocol to reduce data transfer costs and transmission energy consumption. Copyright © 2014 John Wiley & Sons, Ltd.     

Analyzing the Effects of Hyperthreading on the Performance of Data Management Systems

As information processing applications take greater roles in our everyday life, database management systems (DBMSs) are growing in importance. DBMSs have traditionally exhibited poor cache performance and large memory footprints, therefore performing only at a fraction of their ideal execution and exhibiting low processor utilization. Previous research has studied the memory system of DBMSs on research-based simultaneous multithreading (SMT) processors. Recently, several differences have been noted between the real hyper-threaded architecture implemented by the Intel Pentium 4 and the earlier SMT research architectures. This paper characterizes the performance of a prototype open-source DBMS running TPC-equivalent benchmark queries on an Intel Pentium 4 Hyper-Threading processor. We use hardware counters provided by the Pentium 4 to evaluate the micro-architecture and study the memory system behavior of each query running on the DBMS. Our results show a performance improvement of up to 1.16 in TPC-C-equivalent and 1.26 in TPC-H-equivalent queries due to hyperthreading.     

Wear resistance of δ-type aluminafibre reinforced Al-4% Cu matrix composite

The wear behaviour of Al-4% Cu alloy and its composite containing-type alumina fibres has been studied at roomtemperature and at 150°C, using a standard pin-on-ringtribometer. The results show higher wear resistance and a lowercoefficient of friction for the composite material as comparedwith the matrix alloy. Three wear mechanisms of the matrix alloytested at room temperature were observed: oxidation-induceddelamination, seizure and subsequent wear due to surfacemelting. At 150°C, however, the matrix wear is due toseizure and melting. In the case of the composite material,different wear mechanisms were found: at low loads, oxidation-induced delamination was predominant, changing to high-strain-induced delamination at higher loads up to 80 N; at high loads(beyond 120 N) sub-surface delamination was the prevailingmechanism.     

铁对粉末冶金法制备铝基复合材料微观组织和力学性能及磁学性能的影响(英文)

研究铁对粉末冶金法制备铝基复合材料微观组织、力学性能及磁学性能的影响。利用机械混合制备含0,5%,10%和15%Fe(质量分数)的铝基复合材料。Al-Fe混合粉末经压制后在真空炉中600°C烧结1 h。XRD结果表明:在含有5%和10%Fe的试样中只有Fe和Al的衍射峰,而含有15%Fe的试样中则存在Al和Al13Fe4的衍射峰。实验结果表明:随着Fe含量的增加,材料的致密度和导热性变差。复合材料中的Fe可以提高其强度和硬度。材料的强化机制包括基体的晶粒细化,Fe颗粒的均匀分布以及Al13Fe4金属间化合物的形成。含有5%Fe试样的磁化强度为0.3816×10-3A·m2/g,对于含有10%Fe的试样,其磁化强度增加至0.6597×10-3A·m2/g,而对于含有15%Fe试样,其磁化强度降低至0.0702×10-3A·m2/g。这是由于在高铁试样中形成了反磁性的Al13Fe4金属间化合物导致磁化强度降低。