THEORETICAL STUDY OF NONUNIFORM DROPLETS CONCENTRATION DISTRIBUTION ON VENTURI SCRUBBER PERFORMANCE

A new three-dimensional dispersion model has been developed and was used to study particulate removal operations in a venturi type scrubber. The model takes into account the effect of nonuniform droplets concentration distribution on the particulate removal efficiency of the scrubber of Brink and Contant (1958). Experimental data was used to test the results of the mathematical model. The results from the model are in good agreement with the experimental data. After validating the model, it was used to predict the effect of parameters such as liquid to gas flow rate ratio, gas throat velocity, and angle of the divergent section and nozzle diameter on the extent of nonuniformity of drops. Removal efficiency will increase with increasing uniformity of droplets concentration distribution. Thus, any factor that increases removal efficiency increases uniformity and vice versa. The factors affecting uniformity are: droplet diameter, liquid jet penetration length and size of scrubber.     

Generalized carrier to interference ratio analysis for shotgun cellular systems in multiple dimensions over composite Rayleigh–Lognormal (Suzuki) fading

Telecommunication Systems - This paper analyzes the carrier-to-interference ratio (CIR) of the so-called shotgun cellular systems (SCSs) in $$\tau $$ dimensions ( $$\tau =1, 2,$$ and 3). SCSs are...     

Wideband Frequency-Reconfigurable Antenna for Airborne Applications

Wireless Personal Communications - One of the important objectives of underwater acoustic sensor network is to extend the lifespan of a network which depends on the topology control mechanisms....     

Time-Domain Block and Per-Tone Equalization for MIMO–OFDM in Shallow Underwater Acoustic Communication

Shallow underwater acoustic (UWA) channel exhibits rapid temporal variations, extensive multipath spreads, and severe frequency-dependent attenuations. So, high data rate communication with high spectral efficiency in this challenging medium requires efficient system design. Multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO–OFDM) is a promising solution for reliable transmission over highly dispersive channels. In this paper, we study the equalization of shallow UWA channels when a MIMO–OFDM transmission scheme is used. We address simultaneously the long multipath spread and rapid temporal variations of the channel. These features lead to interblock interference (IBI) along with intercarrier interference (ICI), thereby degrading the system performance. We describe the underwater channel using a general basis expansion model (BEM), and propose time-domain block equalization techniques to jointly eliminate the IBI and ICI. The block equalizers are derived based on minimum mean-square error and zero-forcing criteria. We also develop a novel approach to design two time-domain per-tone equalizers, which minimize bit error rate or mean-square error in each subcarrier. We simulate a typical shallow UWA channel to demonstrate the desirable performance of the proposed equalization techniques in Rayleigh and Rician fading channels.     

A Low-Voltage Fully Differential Pure Current Mode Current Operational Amplifier

In this paper a novel high-frequency fully differential pure current mode current operational amplifier (COA) is proposed that is, to the authors’ knowledge, the first pure MOSFET Current Mode Logic (MCML) COA in the world, so far. Doing fully current mode signal processing and avoiding high impedance nodes in the signal path grant the proposed COA such outstanding properties as high current gain, broad bandwidth, and low voltage and low-power consumption. The principle operation of the block is discussed and its outstanding properties are verified by HSPICE simulations using TSMC \(0.18\,\upmu \hbox {m}\) CMOS technology parameters. Pre-layout and Post-layout both plus Monte Carlo simulations are performed under supply voltages of \(\pm 0.75\,\hbox {V}\) to investigate its robust performance at the presence of fabrication non-idealities. The pre-layout plus Monte Carlo results are as; 93 dB current gain, \(8.2\,\hbox {MHz}\,\, f_{-3\,\text {dB}}, 89^{\circ }\) phase margin, 137 dB CMRR, 13 \(\Omega \) input impedance, \(89\,\hbox {M}\Omega \) output impedance and 1.37 mW consumed power. Also post-layout plus Monte Carlo simulation results (that are generally believed to be as reliable and practical as are measuring ones) are extracted that favorably show(in abovementioned order of pre-layout) 88 dB current gain, \(6.9\,\hbox {MHz} f_{-3\text {db}} , 131^{\circ }\) phase margin and 96 dB CMRR, \(22\,\Omega \) input impedance, \(33\,\hbox {M}\Omega \) output impedance and only 1.43 mW consumed power. These results altogether prove both excellent quality and well resistance of the proposed COA against technology and fabrication non-idealities.     

A wide frequency range delay line for fast-locking and low power delay-locked-loops

A voltage controlled delay cell with wide frequency range is presented in this paper. The delay-line which is resulted by connecting five series of delay cells generating a wide range of delay from 1.9 to 13.24 ns. It can be used in an analog delay locked loop. The linear characteristic of the circuit with respect to the conventional delay line structures is improved, and a better performance of noise is obtained using differential structure. This circuit is designed by ADS software and TSMC CMOS 0.18 μm technology, with supply voltage 1.8 V. By changing control voltage from 0.335 to 1.8 V in delay line, a wide range of frequency from 75.52 to 917.43 MHz will be covered. Simulation results show that the proposed delay line has power consumption of maximum 3.77 mW at frequency of 75.52 MHz. It also shows that increasing of frequency will reduce power dissipation which is the one of the main characteristics of this novel circuit. Moreover, the delay locked loop which uses these delay cells has a very high lock speed so that the maximum lock time in just five clock cycles.     

Highly Conductive Carbon Nanotube‐Graphene Hybrid Yarn

An efficient procedure for the fabrication of highly conductive carbon nanotube/graphene hybrid yarns has been developed. To start, arrays of vertically aligned multi‐walled carbon nanotubes (MWNT) are converted into indefinitely long MWNT sheets by drawing. Graphene flakes are then deposited onto the MWNT sheets by electrospinning to form a composite structure that is transformed into yarn filaments by twisting. The process is scalable for yarn fabrication on an industrial scale. Prepared materials are characterized by electron microscopy, electrical, mechanical, and electrochemical measurements. It is found that the electrical conductivity of the composite MWNT‐graphene yarns is over 900 S/cm. This value is 400% and 1250% higher than electrical conductivity of pristine MWNT yarns or graphene paper, respectively. The increase in conductivity is asssociated with the increase of the density of states near the Fermi level by a factor of 100 and a decrease in the hopping distance by an order of magnitude induced by grapene flakes. It is found also that the MWNT‐graphene yarn has a strong electrochemical response with specific capacitance in excess of 111 Fg^?1. This value is 425% higher than the capacitance of pristine MWNT yarn. Such substantial improvements of key properties of the hybrid material can be associated with the synergy of MWNT and graphene layers in the yarn structure. Prepared hybrid yarns can benefit such applications as high‐performance supercapacitors, batteries, high current capable cables, and artificial muscles.     

All two-input logic gates by a single-stage single electron box

In this paper, the design of all two-input logic gates is presented by only a single-stage single electron box (SEB) for the first time. All gates are constructed based on a same circuit. We have used unique periodic characteristics of SEB to design these gates and present all two-input logic gates (monotonic/non-monotonic, symmetric/non-symmetric) by a single-stage design. In conventional monotonic devices, such as MOSFETs, implementing non-monotonic logic gates such as XOR and XNOR is impossible by only a single-stage design, and a multistage design is required which leads to more complexity, higher power consumption and less speed of the gates. We present qualitative design at first and then detailed designs are investigated and optimised by using our previous works. All designs are verified by a single electron simulator which shows correct operation of the gates.