Unraveling the Significance of Li+/e−/O2 Phase Boundaries with a 3D-Patterned Cu Electrode for Li–O2 Batteries

The reaction kinetics at a triple-phase boundary (TPB) involving Li⁺, e⁻, and O₂ dominate their electrochemical performances in Li–O₂ batteries. Early studies on catalytic activities at Li⁺/e⁻/O₂ interfaces have enabled great progress in energy efficiency; however, localized TPBs within the cathode hamper innovations in battery performance toward commercialization. Here, the effects of homogenized TPBs on the reaction kinetics in air cathodes with structurally designed pore networks in terms of pore size, interconnectivity, and orderliness are explored. The diffusion fluxes of reactants are visualized by modeling, and the simulated map reveals evenly distributed reaction areas within the periodic open structure. The 3D air cathode provides highly active, homogeneous TPBs over a real electrode scale, thus simultaneously achieving large discharge capacity, unprecedented energy efficiency, and long cyclability via mechanical/electrochemical stress relaxation. Homogeneous TPBs by cathode structural engineering provide a new strategy for improving the reaction kinetics beyond controlling the intrinsic properties of the materials.     

GaAs vertical-cavity surface emitting lasers fabricated by reactive ion etching

GaAs quantum well vertical-cavity surface emitting lasers fabricated using low damage reactive ion etching are discussed. Lasers which are partially and completely etched through their structure are compared. The surface recombination velocity of exposed GaAs is not exacerbated in deep etched lasers; other loss mechanisms in shallow etched lasers have comparable impact on laser performance. Etched lasers exhibit low voltage and small differential series resistance at threshold, while devices fabricated by a combination of etching and ion implantation possess lower threshold current. It is found that reactive ion etching has little additional effect on laser operation, whereas the different device structures considered do influence laser performance.<>     

New single-stage low dc bus voltage stress converter for universal line applications

A new single-stage power factor corrected ac–dc converter for universal line applications is proposed in this paper. This converter has a buck topology as a power factor corrector. The dc bus voltage of the proposed converter is always lower than the peak input voltage at any load condition. Therefore, the problem of high dc bus voltage under the light load condition for the single-stage converter is solved, especially in the case of universal line applications. The design equations are presented for the proposed converter and a design example for a 5V 12A application is presented. The theoretical analysis and experimental results show that the dc bus voltage can be limited within 260V and the line input current harmonics can meet IEC 61000-3-2 Class D requirements at any load conditions for the line input voltages from 90 to 260V_ac.     

Human action recognition employing negative space features

We proposed a region based method to recognize human actions from video sequences. Unlike other region based methods, it works with the surrounding regions of the human silhouette termed as negative space. This paper further extends the idea of negative space to cope with the changes in viewpoints. It also addresses the problem of long shadows which is one of the major challenges of human action recognition. Some systems attempt suppressing shadows during the segmentation process but our system takes input of segmented binary images of which the shadow is not suppressed. This makes our system less dependent on segmentation process. Further, this approach can complement the positive space (silhouette) based methods to boost recognition. The system consists of a hierarchical processing: histogram analysis on segmented input image, followed by motion and shape feature extraction, pose sequence analysis by employing Dynamic Time Warping and at last classification by Nearest Neighbor classifier. We evaluated our system by most commonly used datasets and achieved higher accuracy than the state of the arts methods. Our system can also retrieve video sequences from queries of human action sequences.     

A novel robust and low cost chips package and its thermalperformance

In an attempt to provide a high density memory solution, especially for workstation and PC servers, a stack chips package (SCP) has been developed. The major characteristics of SCP are as follows: (1) SCP contains a plurality of both memory chips and lead frames within a molded plastic package; (2) chip selection is made through the wire bonding option, resulting in the package with a memory capacity twice or four times that of monolithic chip; (3) plural lead frames are electrically interconnected all at once, using metal solders electroplated on the lead frame surface; and (4) SCP is found reliable and cost competitive when compared to other stack packages because it basically adopts the molded plastic packaging technology as well as the metal solder interconnection method. As electrical interconnection methods, both a fluxless soldering joint of Ag/Sn and a high-pressure mechanical joint of Ag were evaluated extensively and they successfully provided a reliable electrical conduction path without any signal degradation. Temperature cycle test and pressure cooker test were proved not to produce any micro cracks across the joint. The thermal performance of SCP was simulated by a thermal model based on finite element method (FEM) and also experimentally verified, showing good agreement within 10% deviation from simulated value. 128M SCP showed better thermal performance than stacked two TSOP's because one chip could serve as a heat sink while the other chip is activated and thermal conduction path through the lead frame is short     

Interfacial reaction between 42Sn-58Bi solder and electroless Ni-P/immersion Au under bump metallurgy during aging

The interfacial reaction between 42Sn-58Bi solder (in wt.% unless specified otherwise) and electroless Ni-P/immersion Au was investigated before and after thermal aging, with a focus on the formation and growth of an intermetallic compound layer, consumption of under bump metallurgy (UBM), and bump shear strength. The immersion Au layer with thicknesses of 0 μm (bare Ni), 0.1 μm, and 1 μm was plated on a 5-μm-thick layer of electroless Ni-P (with 14–15 at.% P). The 42Sn-58Bi solder balls were then fabricated on three different UBM structures by using screen printing and pre-reflow. A Ni₃Sn₄ layer formed at the joint interface after the pre-reflow for all three UBM structures. On aging at 125°C, a quaternary phase, identified as Sn₇₇Ni₁₅Bi₆Au₂, was observed above the Ni₃Sn₄ layer in the UBM structures that contain Au. The thick Sn₇₇Ni₁₅Bi₆Au₂ layer degraded the integrity of the solder joint, and the shear strength of the solder bump was about 40% less than the nonaged joints.     

High-speed driving method using bipolar scan waveform in AC plasma display panel

This paper proposes a new high-speed driving method using the bipolar scan waveform with a scan width of 1 /spl mu/s in an ac-plasma display panel. The bipolar scan waveform in an address period consists of a two-step pulse with two different polarities, i.e., a forward scan pulse with a negative polarity and reverse scan pulse with a positive polarity, which can produce two address discharges, including a primary address discharge for generating wall charges and secondary address discharge for accumulating wall charges. To produce the fast address discharge stably using the bipolar scan pulse during an address period, a new reset waveform is designed based on a V/sub t/ close curve analysis, and the address discharge characteristics examined under various reset and address waveforms. As a result of adopting the proposed driving method, a high-speed address with a scan width of 1 /spl mu/s is successfully obtained when using a checkered pattern on a 4-in test panel.     

Facile Fabrication and Superparamagnetism of Silica‐Shielded Magnetite Nanoparticles on Carbon Nitride Nanotubes

Using conventional methods to synthesize magnetic nanoparticles (NPs) with uniform size is a challenging task. Moreover, the degradation of magnetic NPs is an obstacle to practical applications. The fabrication of silica‐shielded magnetite NPs on carbon nitride nanotubes (CNNTs) provides a possible route to overcome these problems. While the nitrogen atoms of CNNTs provide selective nucleation sites for NPs of a particular size, the silica layer protects the NPs from oxidation. The morphology and crystal structure of NP–CNNT hybrid material is investigated by transmission electron microscopy (TEM) and X‐ray diffraction. In addition, the atomic nature of the N atoms in the NP–CNNT system is studied by near‐edge X‐ray absorption fine structure spectroscopy (nitrogen K‐edge) and calculations of the partial density of states based on first principles. The structure of the silica‐shielded NP–CNNT system is analyzed by TEM and energy dispersive X‐ray spectroscopy mapping, and their magnetism is measured by vibrating sample and superconducting quantum interference device magnetometers. The silica shielding helps maintain the superparamagnetism of the NPs; without the silica layer, the magnetic properties of NP–CNNT materials significantly degrade over time.     

Effects of channel thickness variation on bias stress instability of InGaZnO thin-film transistors

Here, we report on the effects of channel (or active) layer thickness on the bias stress instability of InGaZnO (IGZO) thin-film transistors (TFTs). The investigation on variations of TFT characteristics under the electrical bias stress is very crucial for commercial applications. In this work, the initial electrical characteristics of the tested TFTs with different channel layer thicknesses (40, 50, and 60 nm) are performed. Various gate bias (V_GS) stresses (10, 20, and 30 V) are then applied to the tested TFTs. For all V_GS stresses with different channel layer thickness, the experimentally measured threshold voltage shift (ΔV_th) as a function of stress time is precisely modeled with stretched-exponential function. It is indicated that the ΔV_th is generated by carrier trapping but not defect creation. It is also observed that the ΔV_th shows incremental behavior as the channel layer thickness increases. Thus, it is verified that the increase of total trap states (N_T) and free carriers resulted in the increase of ΔV_th as the channel layer thickness increases.