Inverter Nonlinearity Compensation in the Presence of Current Measurement Errors and Switching Device Parameter Uncertainties

This paper proposes a compensation strategy for the unwanted disturbance voltage due to inverter nonlinearity. We employ an emerging learning technique called support vector regression (SVR). SVR constructs a motor dynamic voltage model by a linear combination of the current samples in real time. The model exhibits fast observer dynamics and robustness to observation noise. Then the disturbance voltage is estimated by subtracting the constructed voltage model from the current controller output. The proposed method compensates for all of the inverter nonlinearity factors at the same time. All the processes in estimating distortions are independent of the dead time and power device parameters. From the analysis of the effect on current measurement errors, we confirmed that the sampling error had little negative impact on the proposed estimation method. Experiments demonstrate the superiority of the proposed method in suppressing voltage distortions caused by inverter nonlinearity     

Over-erase phenomenon in SONOS-type flash memory and its minimization using a hafnium oxide charge storage Layer

The over-erase phenomenon in the polysilicon-oxide-silicon nitride-oxide-silicon (SONOS) memory structure is minimized by using hafnium oxide or hafnium aluminum oxide to replace silicon nitride as the charge storage layer (the resulting structures are termed SOHOS devices, where the "H" denotes the high dielectric constant material instead of silicon nitride). Unlike SONOS devices, SOHOS structures show a reduced over-erase phenomenon and self-limiting charge storage behavior under both erase and program operations. These are attributed to the differences in band offset and the crystallinity of the charge storage layer.     

Laser Process Proximity Correction for Improvement of Critical Dimension Linearity on a Photomask

We report on the improvement of critical dimension (CD) linearity on a photomask by applying the concept of process proximity correction to a laser lithographic process used for the fabrication of photomasks. Rule‐based laser process proximity correction (LPC) was performed using an automated optical proximity correction tool and we obtained dramatic improvement of CD linearity on a photomask. A study on model‐based LPC was executed using a two‐Gaussian kernel function and we extracted model parameters for the laser lithographic process by fitting the model‐predicted CD linearity data with measured ones. Model‐predicted bias values of isolated space (I/S), arrayed contact (A/C) and isolated contact (I/C) were in good agreement with those obtained by the nonlinear curve‐fitting method used for the rule‐based LPC.     

Reset-while-address (RWA) driving scheme for high-speed address in AC plasma display panel with high Xe content

A new reset while-address (RWA) driving scheme for a single scan of an XGA grade (1024 /spl times/ 768) ac-plasma display panel (PDP) is proposed to improve the address discharge characteristics with a high Xe gas mixture (15%). To solve the conventional address problem of the gradual decrease in priming particles during an address period, the falling ramp waveform in the reset period is separated into two parts; the first part is applied at the beginning of the reset period and provides the priming particles during the first half of the address period, while the second part is applied in the middle of the address period to provide an additional supply of priming particles during the second half of the address period. As a result of adopting the proposed RWA driving scheme, address discharges were successfully produced within a 1.0-/spl mu/s pulsewidth due to the presence of priming particles throughout the address period.     

Optimal rebinning of time-of-flight PET data

Time-of-flight (TOF) positron emission tomography (PET) scanners offer the potential for significantly improved signal-to-noise ratio (SNR) and lesion detectability in clinical PET. However, fully 3D TOF PET image reconstruction is a challenging task due to the huge data size. One solution to this problem is to rebin TOF data into a lower dimensional format. We have recently developed Fourier rebinning methods for mapping TOF data into non-TOF formats that retain substantial SNR advantages relative to sinograms acquired without TOF information. However, mappings for rebinning into non-TOF formats are not unique and optimization of rebinning methods has not been widely investigated. In this paper we address the question of optimal rebinning in order to make full use of TOF information. We focus on FORET-3D, which approximately rebins 3D TOF data into 3D non-TOF sinogram formats without requiring a Fourier transform in the axial direction. We optimize the weighting for FORET-3D to minimize the variance, resulting in H(2)-weighted FORET-3D, which turns out to be the best linear unbiased estimator (BLUE) under reasonable approximations and furthermore the uniformly minimum variance unbiased (UMVU) estimator under Gaussian noise assumptions. This implies that any information loss due to optimal rebinning is as a result only of the approximations used in deriving the rebinning equation and developing the optimal weighting. We demonstrate using simulated and real phantom TOF data that the optimal rebinning method achieves variance reduction and contrast recovery improvement compared to nonoptimized rebinning weightings. In our preliminary study using a simplified simulation setup, the performance of the optimal rebinning method was comparable to that of fully 3D TOF MAP.     

Miniaturisation and high quality factor of spiral meander spurline resonator for microwave oscillator

The spiral meander spurline structure is an optimal solution for a reduced resonator size and a high Quality factor (Q-factor) compared to other conventional spurline structures. The spiral meander spurline resonator shows not only 38% reduced dimensional effect, but also 16% improved Q-factor compared with conventional meander spurline resonator. Moreover, in order to get more high quality factor, we analysed spurline slot width variation and designed the symmetric dual spiral meander structure, which has a 46.87% improved Q-factor compare with a single spiral meander. The symmetric dual spiral meander structure resonator performance results are shown in a return loss of ?0.76?dB, an insertion loss of ?46.32?dB, and a quality factor of 235 at 6.4?GHz C-band application. In addition, according to the design and performance of the resonator, we can derive from this performance a low phase noise oscillator. The oscillators using symmetric dual spiral meander structure resonator shows good phase noise performances of ?104.43?dBc/Hz at a 100?kHz offset from the carrier frequencies of 6.38?GHz at output powers of 12.2?dBm, respectively.     

Versatile threshold voltage control of OTFTs via discontinuous pn-heterojunction formation

We demonstrate the versatility of the threshold voltage control for organic thin-film transistors (OTFTs) based on formation of discontinuous pn-heterojunction on the active channel layer. By depositing n-type dioctyl perylene tetracarboxylic diimide molecules discontinuously onto base p-type pentacene thin films (the formation of the discontinuous pn-heterojunction), a positive shift of the threshold voltage was attained which enabled realizing a depletion-mode transistor from an original enhancement-mode pristine pentacene transistor. Careful control of the threshold voltage based on this method led assembling a depletion-load inverter comprising a depletion-mode transistor and an enhancement-mode transistor connected in series that yielded tunable signal inversion voltage approaching 0 V. In addition, the tunability could be applied to improve the program/erase signal ratio for non-volatile transistor memories by more than 4 orders of magnitude compared to reference memory devices made of pristine pentacene transistors.     

Energy Efficient Broadcast in Wireless Ad hoc Networks with Hitch-hiking

In this paper, we propose a novel concept called Hitch-hiking in order to reduce the energy consumption of broadcast application for wireless networks. Hitch-hiking takes advantage of the physical layer design that facilitates the combining of partial signals to obtain the complete information. The concept of combining partial signals using maximal ratio combiner [15] has been used to improve the reliability of the communication link but has never been exploited to reduce energy consumption in broadcasting over wireless ad hoc networks. We study the advantage of Hitch-hiking for the scenario when the transmission power level of nodes is fixed as well as the scenario when the nodes can adjust their power level. For both scenarios, we show that Hitch-hiking is advantageous and have proposed algorithms to construct broadcast tree with Hitch-hiking taken into consideration. For fixed transmission power case, we propose and analyze a centralized heuristic algorithm called SPWMH (Single Power Wireless Multicast with Hitch-hiking) to construct a broadcast tree with minimum forwarding nodes. For the latter case, we propose a centralized heuristic algorithm called Wireless Multicast with Hitch-hiking (WMH) to construct an energy efficient tree using Hitch-hiking and also present a distributed version of the heuristic. We also evaluate the proposed heuristics through simulation. Simulation results show that Hitch-hiking can reduce the transmission cost of broadcast by as much as 50%. Further, we propose and evaluate a protocol called Power Saving with Broadcast Tree (PSBT) that reduces energy consumption of broadcast by eliminating redundancy in receive operation. Finally, we propose an algorithm that takes advantage of both Hitch-hiking and PSBT in conserving energy. Manish Agarwal is an engineer at Microsoft, Redmond. He received his Masters degree in Electrical and Computer Engineering from University of Massachusetts, Amherst in 2004. He received his undergraduate degree from Indian Institute of Technology, Guwahati. His research interest lies in the field of mobile ad hoc networks. Lixin Gao is an associate professor of Electrical and Computer Engineering at the University of Masschusetts, Amherst. She received her Ph.D. degree in computer science from the University of Massachusettes at Amherst in 1996. Her research interests include multimedia networking and Internet routing. Between May 1999 and January 2000, she was a visiting researcher at AT&T Research Labs and DIMACS. She is an Alfred P. Sloan Fellow and received an NSF CAREER Award in 1999. She is a member of IEEE, ACM, and Sigma Xi. Joon Ho Cho received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, Korea, in 1995 and the M.S.E.E. and Ph.D. degrees in electrical and computer engineering from Purdue University, West Lafayette, IN, in 1997 and 2001, respectively. From 2001 to 2004, he was with the University of Massachusetts at Amherst as an Assistant Professor. Since July 2004, he has been with Pohang University of Science and Technology (POSTECH), Pohang, Korea, where he is presently an Assistant Professor in the Department of Electronic and Electrical Engineering. His research interests include wideband systems, multiuser communications, adaptive signal processing, packet radio networks, and information theory. Dr. Cho is currently an Associate Editor for the IEEE Transactions on Vehicular Technology. Jie Wu is a Professor at Department of Computer Science and Engineering, Florida Atlantic University. He has published over 300 papers in various journal and conference proceedings. His research interests are in the area of mobile computing, routing protocols, fault-tolerant computing, and interconnection networks. Dr. Wu served as a program vice chair for 2000 International Conference on Parallel Processing (ICPP) and a program vice chair for 2001 IEEE International Conference on Distributed Computing Systems (ICDCS). He is a program co-chair for the IEEE 1st International Conference on Mobile Ad-hoc and Sensor Systems (MASS'04). He was a co-guest-editor of a special issue in IEEE Computer on “Ad Hoc Networks”. He also editored several special issues in Journal of Parallel and Distributing Computing (JPDC) and IEEE Transactions on Parallel and Distributed Systems (TPDS). He is the author of the text “Distributed System Design” published by the CRC press. Currently, Dr. Wu serves as an Associate Editor in IEEE Transactions on Parallel and Distributed Systems and three other international journals. Dr. Wu is a recipient of the 1996–97 and 2001–2002 Researcher of the Year Award at Florida Atlantic University. He served as an IEEE Computer Society Distinguished Visitor. Dr. Wu is a Member of ACM and a Senior Member of IEEE.     

A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices

This paper extends the timing test model in [5] to be more realistic by including the effects of the test fixtures between a device under test and a tester. The paper enables analyzing the trade-offs that arise between the predicted yield and the required overall test environment timing accuracy (OTETA) which involves the tester overall timing accuracy (OTA) and the test fixtures' impacts. We specifically focus on the application of the extended model to predict the test yield of standard high-speed interconnects, such as PCI Express, Parallel/Serial RapidIO, and HyperTransport. The extended model reveals that achieving an actual yield of 80% with a test escape of 300 DPM (Defects Per Million) requires an equivalent OTETA that is about half the acceptable absolute limit of the tested parameter. Baosheng Wang received his B.S. degree from Beijing University of Aeronautics and Astronautics (BUAA), Beijing, P.R. China, in 1997 and M.S. degree from Precision Instrument & Mechanical Engineering from the Tsinghua University, Beijing, P. R. China in 2000. In 2005, he received his Ph.D. degree in Electrical Engineering from the University of British Columbia (UBC), Vancouver, BC, Canada. During his Master study, he was doing MEMS, Micro Sensors and Digital Signal processing. From 2000 to 2001, he worked in Beijing Gaohong Telecommunications Company as a hardware engineer in ATM technology. Currently, he is a Design-for-Test (DFT) engineer at ATI Technologies Inc., Markham, Ontario, Canada. He publishes widely at international conferences and journals. His primary research interests are time-driven or timing-oriented testing methodologies for System on-a-Chip (SoC). These fields include test time reduction for SRAMs, accelerated reliability test for non-volatile memories, yield analysis for SoC timing tests, SoC path delay timing characterization and embedded timing measurements. Andy Kuo is currently a Ph.D student of System on a Chip (SoC) Research Lab at the Department of Electrical and Computer Engineering, University of British Columbia. He received his M.A.Sc. and B.A.Sc in electrical and computer engineering from University of British Columbia and University of Toronto in 2004 and 2002 respectively. His research interests include high-speed signal integrity issues, jitter measurement, serial communications. Touraj Farahmand received the B.Sc. degree in Electrical Engineering from Esfahan University of Technology, Esfahan, Iran in 1989 and the M.Sc. in Control Engineering from Sharif university of Technology, Tehran, Iran in 1992. After graduation, he joined the Electrical and Computer Research center of Esfahan University of Technology where he was involved in the DSP algorithm development and design and implementation of the control and automation systems. Since October 2001, he has been working in the area of high-speed signal timing measurement at SoC (System-on-a-Chip) lab of UBC (University of British Columbia) as a research engineer. His research interests are signal processing, jitter measurement, serial communication and control. André Ivanov is Professor in the Department of Electrical and Computer Engineering, at the University of British Columbia. Prior to joining UBC in 1989, he received his B.Eng. (Hon.), M. Eng., and Ph.D. degrees in Electrical Engineering from McGill University. In 1995–96, he spent a sabbatical leave at PMC-Sierra, Vancouver, BC. He has held invited Professor positions at the University of Montpellier II, the University of Bordeaux I, and Edith Cowan University, in Perth, Australia. His primary research interests lie in the area of integrated circuit testing, design for testability and built-in self-test, for digital, analog and mixed-signal circuits, and systems on a chip (SoCs). He has published widely in these areas and holds several patents in IC design and test. Besides testing, Ivanov has interests in the design and design methodologies of large and complex integrated circuits and SoCs. Dr. Ivanov has served and continues to serve on numerous national and international steering, program, and/or organization committees in various capacities. Recently, he was the Program Chair of the 2002 VLSI Test Symposium (VTS'02) and the General Chair for VTS'03 and VTS'04. In 2001, Ivanov co-founded Vector 12, a semiconductor IP company. He has published over 100 papers in conference and journals and holds 4 US patents. Ivanov serves on the Editorial Board of the IEEE Design and Test Magazine, and Kluwer's Journal of Electronic Testing: Theory and Applications. Ivanov is currently the Chair of the IEEE Computer Society's Test Technology Technical Council (TTTC). He is a Golden Core Member of the IEEE Computer Society, a Senior Member of the IEEE, a Fellow of the British Columbia Advanced Systems Institute and a Professional Engineer of British Columbia. Yong Cho received the B.S. degree from Kyung Pook National Unviersity, Korea, in 1981 and the M.S. degree from in electrical and computer engineering from the University of South Carolina, Columbia, S.C., in 1988 and the Ph.D. degree in electrical engineering and applied physics from Case Western Reserve University, Cleveland, OH, in 1992. He is currently a Professor with the Department of Electronics Engineering, Konkuk University, Seoul, Korea. His recent research interests include SoC Design and Verification, H/W and S/W co-design, and embedded programming on SoC. Sassan Tabatabaei received his PHD in Electrical Engineering from the University of British Columbia, Vancouver, Canada in 2000. Since then, he has held several senior technical positions at Vector12 Corp, Guide Technology, and Virage Logic. His professional and research interests include mixed-signal design and test, and signal integrity and jitter test methodologies for high-speed circuits and multi-Gbps serial interfaces. He has published several papers and holds a US patent in the area of timing and jitter measurement. Currently, he holds the position of the director for embedded test at Virage Logic Corporation.