A low power voltage limiter for a full passive UHF RFID sensor on a 0.35 μm CMOS process

This paper presents a low power voltage limiter design for avoiding possible damages in the analog front-end of a RFID sensor due to voltage surges whenever readers and tags are close. The proposed voltage limiter design takes advantage of the implemented bandgap reference and voltage regulator blocks in order to provide low deviation of the limiting voltage due to temperature variation and process dispersion. The measured limiting voltage is 2.9 V with a voltage deviation of only ±0.065 V for the 12 measured dies. The measured current consumption is only 150 nA when the reader and the tag are far away, not limiting the sensitivity of the tag due to an undesired consumption in the voltage limiter. The circuit is implemented on a low cost 2P4M 0.35 μm CMOS technology.     

A visible-light and infrared video database for performance evaluation of video/image fusion methods

Multidimensional Systems and Signal Processing - In general, the fusion of visible-light and infrared images produces a composite representation where both data are pictured in a single image. The...     

Ultrasound image segmentation with shape priors: application to automatic cattle rib-eye area estimation.

Automatic ultrasound (US) image segmentation is a difficult task due to the quantity of noise present in the images and the lack of information in several zones produced by the acquisition conditions. In this paper, we propose a method that combines shape priors and image information to achieve this task. In particular, we introduce knowledge about the rib-eye shape using a set of images manually segmented by experts. A method is proposed for the automatic segmentation of new samples in which a closed curve is fitted taking into account both the US image information and the geodesic distance between the evolving curve and the estimated mean rib-eye shape in a shape space. This method can be used to solve similar problems that arise when dealing with US images in other fields. The method was successfully tested over a database composed of 610 US images, for which we have the manual segmentations of two experts.     

A dynamically reconfigurable monolithic CMOS pressure sensor for smart fabric

This paper presents a mixed-signal system-on-chip (SOC) for sensing capacitance variations, enabling the creation of pressure-sensitive fabric. The chip is designed to sit in the corner of a smart fabric such as elastic foam overlaid with a matrix of conductive threads. When pressure is applied to the matrix, an image is created from measuring the differences in capacitance among the rows and columns of fibers patterned on the two opposite sides of the elastic substrate. The SOC approach provides the flexibility to accommodate for different fabric sizes and to perform image enhancement and on-chip data processing. The chip has been designed in a 0.35-/spl mu/m five-metal one-poly CMOS process working up to 40 MHz at 3.3 V of power supply, in a fully reconfigurable arrangement of 128 I/O lines. The core area is 32 mm/sup 2/.     

A Privacy-Considerate Framework for Identity Management in Mobile Services

The subscribers’ personal information and services that mobile operators are able to provide to Web developers offer new and exciting possibilities in numerous domains. However, bringing mobile information services to the Web to enable a new generation of mobile Web services presents several research challenges on identity and privacy management. In this paper, we describe a framework for identity management in mobile services that empowers users to govern the use and release of their personal information. Our framework is based on a brokering approach that intermediates between the mobile operator’s information services and the Web service providers. By leveraging on Web services, identity management infrastructure and privacy enhancing technologies, our framework provides an effective, privacy-considerate delivery of services over the mobile Web environment. This paper describes the design principles and architecture of the framework as well as the feasibility, applicability and user-experience evaluation we have carried out.     

Improved Thermal Behavior of Multiple Linked Arrays of Silicon Nanowires Integrated into Planar Thermoelectric Microgenerators

Low-dimensional structures have been shown to be promising candidates for enhancing the thermoelectric properties of semiconductors, paving the way for integration of thermoelectric generators into silicon microtechnology. With this aim, dense arrays of well-oriented and size-controlled silicon nanowires (Si NWs) obtained by the chemical vapor deposition (CVD)-vapor–liquid–solid (VLS) mechanism have been implemented into microfabricated structures to develop planar unileg thermoelectric microgenerators (μTEGs). Different low-thermal-mass suspended structures have been designed and microfabricated on silicon-on-insulator (SOI) substrates to operate as microthermoelements using p-type Si NW arrays as the thermoelectric material. To obtain nanowire arrays with effective lengths larger than normally attained by the VLS technique, structures composed of multiple ordered arrays consecutively bridged by transversal microspacers have been fabricated. The successive linkage of multiple Si NW arrays enabled the development of larger temperature differences while preserving good electrical contact. This gives rise to small internal thermoelement resistances, enhancing the performance of the devices as energy harvesters.     

Evidence for the Band‐Edge Exciton of CuInS2 Nanocrystals Enables Record Efficient Large‐Area Luminescent Solar Concentrators

Ternary I‐III‐VI₂ nanocrystals (NCs), such as CuInS₂, are receiving attention as heavy‐metals‐free materials for solar cells, luminescent solar concentrators (LSCs), LEDs, and bio‐imaging. The origin of the optical properties of CuInS₂ NCs are however not fully understood. A recent theoretical model suggests that their characteristic Stokes‐shifted and long‐lived luminescence arises from the structure of the valence band (VB) and predicts distinctive optical behaviours in defect‐free NCs: the quadratic dependence of the radiative decay rate and the Stokes shift on the NC radius. If confirmed, this would have crucial implications for LSCs as the solar spectral coverage ensured by low‐bandgap NCs would be accompanied by increased re‐absorption losses. Here, by studying stoichiometric CuInS₂ NCs, it is revealed for the first time the spectroscopic signatures predicted for the free band‐edge exciton, thus supporting the VB‐structure model. At very low temperatures, the NCs also show dark‐state emission likely originating from enhanced electron‐hole spin interaction. The impact of the observed optical behaviours on LSCs is evaluated by Monte Carlo ray‐tracing simulations. Based on the emerging device design guidelines, optical‐grade large‐area (30×30 cm²) LSCs with optical power efficiency (OPE) as high as 6.8% are fabricated, corresponding to the highest value reported to date for large‐area devices.     

Material requirements for the adoption of unconventional silicon crystal and wafer growth techniques for high‐efficiency solar cells

Silicon wafers comprise approximately 40% of crystalline silicon module cost and represent an area of great technological innovation potential. Paradoxically, unconventional wafer‐growth techniques have thus far failed to displace multicrystalline and Czochralski silicon, despite four decades of innovation. One of the shortcomings of most unconventional materials has been a persistent carrier lifetime deficit in comparison to established wafer technologies, which limits the device efficiency potential. In this perspective article, we review a defect‐management framework that has proven successful in enabling millisecond lifetimes in kerfless and cast materials. Control of dislocations and slowly diffusing metal point defects during growth, coupled to effective control of fast‐diffusing species during cell processing, is critical to enable high cell efficiencies. To accelerate the pace of novel wafer development, we discuss approaches to rapidly evaluate the device efficiency potential of unconventional wafers from injection‐dependent lifetime measurements. Copyright © 2015 John Wiley & Sons, Ltd.     

Internal Geometry Variation of LTCC Inductors to Improve Light-Load Efficiency of DC-DC Converters

A low-profile power inductor fabricated using low-temperature cofired ceramic (LTCC) technology has been demonstrated to improve the light-load efficiency of a converter, without the use of additional control circuitry. This is brought about by the material and the geometry, which causes a change in inductance with load current. Variation in inductor geometry is performed experimentally to study the effects on the light-load efficiency of a converter. By decreasing the conductor width of the inductor, the light-load efficiency can be further improved by 30% in comparison with using commercial inductors of similar inductance. Sufficient core thickness is necessary to have sufficient inductance, since an inductance value which is too low is detrimental from the system power loss point of view, as demonstrated experimentally. From the circuit point of view, there seems to be a critical inductance value, whereby increasing the inductance further, does not result in significant improvement in power stage efficiency. Changing conductor thickness in the range of 260 to 550 mum does not result in significant improvement in the overall efficiency of the converter. Variation in the number of parallel conductors in a multiconductor structure does not have significant effect on light-load efficiency improvement.