Tri-Gate Bulk MOSFET Design for CMOS Scaling to the End of the Roadmap

A tri-gate bulk MOSFET design utilizing a low-aspect-ratio channel is proposed to provide an evolutionary pathway for CMOS scaling to the end of the roadmap. 3-D device simulations indicate that this design offers the advantages of a multi-gate FET (reduced variability in performance and improved scalability) together with the advantages of a conventional planar MOSFET (low substrate cost and capability for dynamic threshold-voltage control).     

Study on the c-axis preferred orientation of ZnO film on various metal electrodes

ZnO thin film was deposited on various metal electrodes by reactive sputtering, and c-axis preferred orientation of the film has been studied. ZnO, which has high piezoelectricity, is promising for oscillators or filter devices such as surface acoustic wave (SAW) device, gas sensor, and film bulk acoustic resonator (FBAR). But, for the application of ZnO film for these devices, the film should be grown with c-axis normal to the electrode. In this study, Pt, Al, and Au were deposited on Si wafer, and the surface roughness and crystal structure of the ZnO film on the electrode were investigated using AFM, scanning electron microscopy (SEM), and X-ray diffraction (XRD). Columnar structures of ZnO films were grown with c-axis normal to all electrodes, and among them Pt electrode showed the highest preferred orientation of ZnO film.     

Structuring communication software for quality-of-serviceguarantees

We propose architectural mechanisms for structuring host communication software to provide QoS guarantees. We present and evaluate a QoS sensitive communication subsystem architecture for end hosts that provides real time communication support for generic network hardware. This architecture provides services for managing communication resources for guaranteed QoS (real time) connections, such as admission control, traffic enforcement, buffer management, and CPU and link scheduling. The architecture design is based on three key goals: maintenance of QoS guarantees on a per connection basis, overload protection between established connections, and fairness in delivered performance to best effort traffic. Using this architecture we implement real time channels, a paradigm for real time communication services in packet switched networks. The proposed architecture features a process per channel model that associates a channel handler with each established channel. The model employed for handler execution is one of “cooperative” preemption, where an executing handler yields the CPU to a waiting higher priority handler at well defined preemption points. The architecture provides several configurable policies for protocol processing and overload protection. We present extensions to the admission control procedure for real time channels to account for cooperative preemption and overlap between protocol processing and link transmission at a sending host. We evaluate the implementation to demonstrate the efficacy with which the architecture maintains QoS guarantees on outgoing traffic while adhering to the stated design goals     

Fast DCT algorithm with fewer multiplication stages

A novel fast DCT scheme with reduced multiplication stages and fewer additions and multiplications is proposed. The proposed algorithm is structured so that most multiplications tend to be performed at the final stage, which reduces the propagation error that could occur in the fixed-point computation. Minimisation of the multiplication stages can further decrease the error     

Room temperature characterization of Hg1-xCdxTe P-on-n heterostructure photodiodes

Measurements of 77K R_oA and 300K reverse bias dynamic impedance (R_dA) products at one volt reverse bias has been carried out to assess the degree of correlation of this figure of merit. Planar P-on-n heterostructures were grown on near lattice-matched CdZnTe substrates with Hg_1-xCd_xTe (0.20< x <0.30) by molecular beam epitaxy. These devices were passivated with CdTe and doped with indium and arsenic as n- and p-type dopants, respectively. Current-voltage characteristic of these devices exhibit thermally generated dark currents at small and modest reverse bias. We have observed that R_oA values of these long wavelength infrared P-on-n heterostructure photodiodes at 77K correlate with room temperature R_dA values. Diode arrays with high room temperature R_dA values at one volt reverse bias also have high R_oA values at 77K. Similarly, low R_dA values at room temperature indicate poor performance at 77K where deviation from diffusion current occurs at reverse bias of 0.2 to 1 volt at room temperature. The results presented here, for a small samples of devices, demonstrate that room temperature measurements of current-voltage characteristics to evaluate Hg_1-xCd_xTe (0.22< x <0.28) diode performance and array uniformity at lower temperatures can be used. This provides an acceptable criteria for further study at lower temperatures.     

Effect of type of processing on the microstructural features and mechanical properties of Al-Cu/SiC metal matrix composites

In this study, an aluminum based metallic matrix (Al-2wt.% Cu) was reinforced with SiC particulates using a conventional casting technique and a new disintegrated melt deposition technique. Microstructural characterization studies conducted on the samples taken from disintegrated melt deposition technique revealed a more uniform distribution of SiC particulates and good interfacial integrity between SiC particulates and metallic matrix when compared to the conventionally cast composite samples. Results of ambient temperature mechanical tests demonstrate an increase in 0.2% YS and ultimate tensile strength of samples taken from disintegrated melt deposition technique when compared with the unreinforced and conventionally cast composite samples. The results of microstructural characterization and mechanical testing were finally rationalized in terms of the nature of processing technique employed to reinforce Al-2wt.% Cu metallic matrix with SiC particulates.     

1.04 GBd low EMI digital video interface system using small swingserial link technique

In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd     

A 200-MHz complex number multiplier using redundant binaryarithmetic

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05×1.33 mm² using 0.8 μm CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz     

Characterization of the cavity nucleation factor for life prediction under creep-fatigue interaction

It is understood that grain boundary cavitation is one of the detrimental processes for the degradation of materials that reduces the creep-fatigue life at high temperatures. In a previous investigation, a model for life prediction under creep-fatigue conditions was proposed in terms of cavity nucleation and growth. In that model, the cavity nucleation factor (P) was introduced to correlate between the number of cavities and the plastic strain range from which athermal vacancies are generated. It was considered to be a material specific constant which was independent of the experimental conditions. However, in this study, it is found that the cavity nucleation factor is a function of the plastic strain range but is independent of the testing temperature at near 0.5 T _m. In the light of this dependency, a new cavity nucleation factor (P'), is introduced. Using this new cavity nucleation factor (P'), a modified equation for life prediction is proposed, and it is shown that there is good agreement between predicted and experimental lives. Additionally, an interesting approach has been made to find the physical meaning of the new cavity nucleation factor (P'). According to this study, it is suggested that the new cavity nucleation factor, which is regarded as a material specific constant, is found to be strongly related to the density of the grain boundary precipitates with a linear relationship existing between them.