A group theoretic approach to multidimensional filter banks: theoryand applications

In this paper, we provide a new method for analyzing multidimensional filter banks. This method enables us to solve various open problems in multidimensional filter bank characterization and design. The essential element in this new approach is the redefinition of polyphase components. It will be shown that a rich set of mathematical tools, in particular algebraic group theory, will become available for use in the analysis of filter banks. We demonstrate the elegance and power of the tool set by employing it for the characterization of multidimensional filter banks and applying it to two open problems. The first problem is concerned with the development of a general method to design multichannel (⩾2), multidimensional filter banks using transformations, while the second problem is concerned with the derivation of general restrictions on group delays in linear phase filter banks. The treatment of these problems is only an illustration of the power of the tool set of algebraic group theory, employed for the first time in the context of multidimensional filter banks     

Lowpass and bandpass transadmittance filter using operational amplifier pole

A new topology simultaneously implementing lowpass (LP) and bandpass (BP) transadmittance filtering signals using a single operational amplifier (OA), one capacitor, and two resistors is presented. The input impedance is very high which is essential for cascading without employment of buffers. The circuit uses absolute minimum number of active and passive components. The filter employs pole-model of OA and as such has acquired suitability for extended frequency operation. The circuit permits separate adjustment of natural frequency (ω₀) and quality factor (Q) in an orthogonal manner. The circuit has low sensitivity figures unlike the reported single amplifier biquads. The PSPICE simulation results are included.     

皮革防霉剂研制探讨

本文通过不同杀菌组分对皮革上常生长的霉菌作抑菌实验比较,寻找原料易得,合成容易,对环境污染小,高效、广谱低毒的杀菌组分,从而筛选出比较有前途的防毒剂品种     

Design and Implementation of Optical Signal Reinstatement Technique for High DPSK RZ Transceiver Scheme

Wireless Personal Communications - Optical signal reinstatement (OSR) is a common technique used in high-speed communication systems. OSR can be achieved using various techniques such as;...     

Extracellular recordings from patterned neuronal networks using planar microelectrode arrays

Neuronal cell networks have been reconstructed on planar microelectrode arrays (MEAs) from dissociated hippocampal pyramidal neurons. Microcontact printing (microCP) and a photoresist-liftoff method were used to selectively localize poly-L-lysine (PLL) on the surface of MEAs. Haptotaxis led to the organization of the neurons into networks localized adjacent to microelectrodes. Various grids of PLL with 2-25-microm-wide lines spaced by 50-200 microm with 15-25-microm nodes at intersection points were used to guide cell body attachment and neurite outgrowth. Bursting activity with spike amplitude attenuation was observed, and multichannel recordings detected instances of coincident firing activity. Finally, we present here an extracellular recording from a approximately 2 microm bundle of guided neurites.     

Convergence behavior of the first-order time-delay digital tanlockloop

Convergence behavior of the previously proposed time-delay digital tanlock loop (TDTL) is analyzed. The approach is built on the actual number of steps required for the convergence of the phase error to its steady-state value. Unlike the first-order conventional digital tanlock loop (CDTL), the Lipschitz bound of TDTL is not a tight limit for the actual convergence time, especially for higher values of the absolute difference between the initial and the steady-state phase errors. For a frequency step input, the first-order TDTL locks faster than CDTL under suitable arrangement of the loop parameters     

Intelligibility improvements using binaural diverse sub-bandprocessing applied to speech corrupted with automobile noise

The paper reports on experiments assessing the capability of a diverse processing, multi-microphone sub-band adaptive signal processing scheme for improving the intelligibility of speech corrupted with automobile noise. Results from formal listening tests demonstrate a significant improvement in the intelligibility and quality of the processed speech. Spoken digits corrupted with automobile noise at a low and a high signal-to-noise ratio were used with two commercial speech recognisers. The results obtained with the recognisers did not demonstrate any statistically significant improvement due to processing in sub-bands     

A CMOS digitally programmable filter technique for VLSI applications

A novel technique for designing analog CMOS integrated filters is proposed. The technique uses digitally controlled current amplifiers (DCCAs) to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. This paper provides an overview of the possibilities of using the DCCA as the core element in programmable filters. In mixed analog/digital systems, the digital tuning feature of the proposed approach allows direct interfacing with the digital signal processing (DSP) part. Basic building blocks such as digitally programmable amplifiers, integrators, and simulated active inductors are given. Systematic designs of second-order filters are presented. Fully differential architectures of the proposed circuits are developed. Experimental results obtained from 0.5 μm standard CMOS chips are provided.     

Logic Design Validation via Simulation and Automatic Test Pattern Generation

We investigate an automated design validation scheme for gate-level combinational and sequential circuits that borrows methods from simulation and test generation for physical faults, and verifies a circuit with respect to a modeled set of design errors. The error models used in prior research are examined and reduced to five types: gate substitution errors (GSEs), gate count errors (GCEs), input count errors (ICEs), wrong input errors (WIEs), and latch count errors (LCEs). Conditions are derived for a gate to be testable for GSEs, which lead to small, complete test sets for GSEs; near-minimal test sets are also derived for GCEs. We analyze undetectability in design errors and relate it to single stuck-line (SSL) redundancy. We show how to map all the foregoing error types into SSL faults, and describe an extensive set of experiments to evaluate the proposed method. These experiments demonstrate that high coverage of the modeled errors can be achieved with small test sets obtained with standard test generation and simulation tools for physical faults.     

Design and Analysis of Single-Bit Ternary Matched Filter

Wireless Personal Communications - Matched filtering has found its way in many diverse applications such as communication, signal processing and more. The emphasis of this paper is on the design...