Machine Learning Based Resource Utilization and Pre-estimation for Network on Chip (NoC) Communication

Network on chip (NoC) is the solution to solve the problem of larger system on chip and bus based communication system. NoC provides scalable, highly reliable and modular approach for on chip communication and related problems. The wireless communication technologies such as IEEE 802.15.4 Zigbee technology follow mesh, star and cluster tree topology. The paper focuses on the development of machine learning model for design and FPGA synthesis of mesh, ring and fat tree NoC for different cluster size (N = 2, 4, 8, 16, 32, 64, 128 and 256). The fat-tree based topologies incorporate more links near the root of the tree, in order to fulfill the requirement for higher communication demand closer to the root of the tree, as compared to its leafs. It is an indirect topology in which not all routers are identical in terms of number of ports connecting to other routers or elements in the network. The research article presents the use of machine learning techniques to predict the FPGA resource utilization for NoC in advance. The present study helps in NoC chip planning before designing the chip itself by taking into account known hardware design parameters, memory utilization and timing parameters such as minimum and maximum period, frequency support etc. The machine learning is carried out based on multiple linear regression, decision tree regression and random forest regression which estimate the accuracy of the design and good performance. The interprocess communication among nodes is verified using Virtex-5 FPGA, in which data flows in packets and can vary up to ‘n’ bit. The designs are developed in Xilinx ISE 14.2 and simulated in Modelsim 10.1b with the help of VHDL programming language. The developed model has been validated and has performed well on independent test data.     

Secondary Electron Intensity Contrast Imaging and Friction Properties of Micromechanically Cleaved Graphene Layers on Insulating Substrates

We report on the surface properties (friction and work function) of micromechanically cleaved graphene layers placed on thermally gown thick insulating (～295 nm of SiO₂) films on commercial Si (001) substrates. By employing atomic force microscopy (AFM) and scanning electron microscopy with varying primary-electron acceleration voltage (V _acc) in secondary electron imaging (SEI) mode, we determined the coefficient of friction (μ) and electronic work function (Φ), respectively, as functions of the number of graphene layers (n). The friction coefficient was deduced from line scans of friction maps obtained simultaneously while measuring AFM topography. The findings show that supported mono-, bi-, and trilayer graphene all yield similar results (～0.03), in contrast to multilayer (～0.027) and thicker graphite (～0.015) flakes. From the SEI contrast variation, we obtained a reproducible discrete distribution of SE intensity stemming from atomically thick graphene layers on a thick insulating substrate. We were able to determine the number of graphene layers (i.e., n) from the SE intensity contrast or the SE intensity itself. Moreover, we found a distinct linear relationship between the relative SE intensity from the graphene layers and their number, provided a relatively lower V _acc was used. The different contrast in SEI micrographs at lower V _acc is attributed to the fact that the generation of secondary electrons emitted from the graphene was affected by the different work functions corresponding to different n values (or thickness contrast, C). This simple and facile method is superior to the conventional optical method in its capability to characterize graphene over sub-1-μm² areas on various insulating substrates. These results are supplemented by optical microscopy, high-resolution transmission electron microscopy, and Raman spectroscopy and Raman mapping that yield the structural quality (or disorder) of the graphene layers, albeit semiquantitatively.     

Scalability and performance of an agent‐based network management middleware

Rapid growth of computer network sizes and uses necessitate analysis of network application middleware in terms of its scalability as well as performance. In this paper we analyze a distributed network management middleware based on agents that can be dispatched to locations where they can execute close to the managed nodes. The described middleware operates between the network protocol layer and the application layer and uses standard TCP protocol and SNMP probes to interface the network. By aggregating requests from many users into a single agent, our system allows multiple managers to probe problem areas with minimal management traffic overhead. We discuss and quantify the benefits of the described middleware by implementing real‐time network managers using our system. The main result of this paper is a comparison of scalability and efficiency of our agent‐based management middleware and traditional SNMP‐based data collection. To this end, we measured traffic in both real and simulated networks. In the latter case, we designed, used and described here a method of separating simulated application flow into separate subflows to simplify design of simulations. Copyright © 2004 John Wiley & Sons, Ltd.     

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results

Due to technology scaling and increasing clock frequency, problems due to noise effects lead to an increase in design/debugging efforts and a decrease in circuit performance. This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital combinational circuits. These noise effects can propagate through a circuit and create a logic error in a latch or at a primary output. We have developed a mixed-signal test generator, called XGEN, that incorporates classical static values as well as dynamic signals such as transitions and pulses, and timing information such as signal arrival times, rise/fall times, and gate delay. In this paper we first discuss the general framework of the test generation algorithm followed by computational results. Comparison of results with SPICE simulations confirms the accuracy of this approach.     

Constitutive and Aging Behavior of Sn3.0Ag0.5Cu Solder Alloy

We describe double-lap shear experiments on Sn3.0Ag0.5Cu solder alloy, from which fits to Anand's viscoplastic constitutive model, power-law creep model, and to time-hardening primary-secondary creep model are derived. Results of monotonic tests for strain rates ranging from 4.02E-6 to 2.40E-3 s^-1, and creep response at stress levels ranging from 19.5 to 45.6 MPa are reported. Both types of tests were conducted at temperatures of 25degC, 75degC , and 125degC. Following an earlier study where Anand model and time hardening creep parameters for Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu solder alloys were reported, here we report power law model parameters so as to enable a comparison between all three alloys. Primary creep in Sn3.0Ag0.5Cu solder alloy is shown to be significant and are considered in addition to secondary creep and monotonic behavior. Aging influence on behavior is also shown to be significant. On the basis of experimental data, the following four aspects are discussed: 1) difference between testing on bulk versus joint specimen; 2) consistency between the creep and monotonic behaviors; 3) comparison against behaviors of Sn1.0Ag0.5Cu and Sn3.8Ag0.7Cu alloys as well as aganist Sn40Pb, 62Sn36Pb2Ag and 96.5Sn3.5Ag alloys; and 4) comparison of Sn3.0Ag0.5Cu and Sn3.8Ag0.7Cu relative to their aging response.     

Temperature dependent drain current model for Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET for wide operating temperature range

This paper presents two dimensional temperature dependent analytical model of Gate Stack Insulated Shallow Extension Silicon On Nothing (ISESON) MOSFET and compares it with the simulated data using ATLAS 3D device simulator for wide operating temperature i.e. 300–500 K for channel length down to 32 nm technology node. In this work, a temperature dependent analytical expression of drain current for sub-threshold region to saturation region has been developed. Lower sub-threshold slope and reduced leakage current in case of ISESON MOSFET (as compared to ISE and SON) results in better NMOS inverter performance and hence ISESON can be widely used in CCD camera as well as for fast switching applications. Further, we have also investigated the impact of temperature on electrical characteristics of ISESON MOSFET which are important for analog applications.     

Probing the Effects of Nanoscale Architecture on the Mechanical Properties of Hexagonal Silica/Polymer Composite Thin Films

We examine the effects of controlling nanoscale architecture on the tensile properties of honeycomb‐structured silica/polymer composite films. The hexagonal films are produced using evaporation‐induced self‐assembly and uniaxially strained using a home‐built tensile testing apparatus. Significant differences in the yield strain, failure strain, and tensile moduli between the axes parallel and perpendicular to the film‐deposition direction are observed for the thinnest films examined and are attributed to anisotropy in the film nanostructure that is further characterized with transmission electron microscopy and atomic force microscopy. For properly oriented composites, these films have tensile moduli comparable to the Young's modulus of bulk silica but exhibit failure strains that are about an order of magnitude larger than those seen in typical bulk‐silica systems. The yielding and failure processes are explored using X‐ray diffraction and optical microscopy and are characterized by irreversible changes in the nanoscale architecture. We show that tuning the nanoscale architecture can provide control over the tensile properties of composites, allowing for materials with combinations of stiffness and elasticity unachievable in the analogous bulk systems.     

Effect of jammer power on the performance of adaptive arrays

The effect of jammer power on the performance of adaptive arrays is studied. It is shown that the output signal-to-interference-plus-noise ratio (SINR) of an adaptive array is a function of jammer power. In the presence of a wide-band jammer, the output SINR of the array decreases with an increase in jammer power and eventually goes to zero. Unlike continuous wave (CW) jammers, a wide-band jammer does not go through power inversion. Instead, as the jammer power is increased, the interference-to-noise ratio (INR) at the array output shows oscillations. For large jammer power, the output INR increases with an increase in jammer power.     

Stochastic analysis of a two-unit parallel system with partial and catastrophic failures and preventive maintenance

This paper studies a two-unit parallel system with each unit having two types of failure and two modes of operation—normal or partial failure mode. A unit fails either due to change in operating characteristics or due to catastrophe. The system goes for preventive maintenance randomly (in time). Failure rates are constant while repair and (preventive) maintenance rates are general. Using the theory of regenerative and Markov-renewal processes several important measures of reliability are obtained.