A new optimal algorithm for the permutation flow-shop problem and its parallel implementation

This paper describes a new parallel algorithm for solving n-job, m-machine flow-shop problems. The algorithm is basically a parallelization of the usual branch-and-bound method. It also takes advantage of all search method to keep high efficiency of parallel processing, when the sub-problem becomes smaller than certain size. It is shown that its implementation on both nCUBE2 and LUNA88k2 gives very good performance characteristics.     

Simulations of construction learning for neuron-computer resources

It is well known that information processing in the brain depends on neuron systems. Simple neuron systems are neural networks, and their learning methods have been studied. However, we believe that research on large-scale neural network systems is still incomplete. Here, we propose a learning method for millions of neurons as resources for a neuron computer. The method is a type of recurrent path-selection, so the neural network objective must have nesting structures. This method is executed at high speed. When information processing is executed by analogue signals, the accumulation of errors is a grave problem. We equipped a neural network with a digitizer and AD/DA (Analogue Digital) converters constructed of neurons. They retain all information signals and guarantee precision in complex operations. By using these techniques, we generated an image shifter constructed of 8.6 million neurons. We believe that there is the potential to design a neuron computer using this scheme. This work was presented in part at the Fifth International Symposium on Artificial Life and Robotics, Oita, Japan, January 26–28, 2000     

Variable-length segmental transmission line and its design guidelines

Waveform distortion is a serious problem in higher-frequency signals on printed circuit boards (PCBs). To overcome this problem, we have already proposed the segmental transmission line (STL) method, which divides transmission lines into several segments with different line widths. Each line width is adjusted to make the reflection noises cancel each other out in order to minimize the signal distortion. In this research, we first analyze the waveform reshaping mechanism of STL. Next, we apply STL to a dual in-line memory module (DIMM) clock-line for high-speed computers. The results give helpful guidelines for STL designs, which shows the efficiency of STL. This work was presented in part at the 12th International Symposium on Artificial Life and Robotics, Oita, Japan, January 25–27, 2007     

A 60-ns 16-Mb flash EEPROM with program and erase sequencecontroller

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks, in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm×2.0 μm and a chip size of 6.5 mm×18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process     

A 10-GHz 8-b multiplexer/demultiplexer chip set for the SONETSTS-192 system

An ultrahigh-speed 8-b multiplexer (MUX) and demultiplexer (DMUX) chip set has been developed for the synchronous optical network (SONET) next-generation optical-fiber communication systems, which will require data bit rates of about 10 Gb/s. These ICs were designed using three novel concepts: a tree-type architecture giving reliable operation, a dynamic divider with a wide operating range, and a 50-Ω on-chip transmission line with high-speed pulse propagation. They were fabricated using a 0.5-μm WN_x-gate GaAs MESFET process. The DMUX and MUX operated at up to 10.4 and 11.4 GHz, respectively, both with an adequate phase margin of more than 230°     

Lateral phototransistor with low intensity light sensitivity

A lateral phototransistor with stable sensitivity to a light input of the order of 10?3lx was fabricated by a single selective diffusion of boron in n on n+ epitaxial wafer. An extended emitter electrode on SiO2, over a whole emitter-base surface junction is employed to obtain stable low-level current gain.     

承受高压及轴向应变的高性能输气管线用钢管的开发和性能分析(中)

近50年来,天然气的消耗量大大增加,并且会继续增加以降低主要能源的CO2排放量。随着天然气供应量的增加,为保证其输送的经济性和安全性,开发了高强度大直径焊管,并已成功应用在全球多个地区（如北极地区、地震带和深海海域）。天然气需求的增加对长距离输送管线用钢管提出了新的要求,为此,研究了更为恶劣环境下承受高压和轴向应变的高性能钢管：分析了所开发的高压输气管线用高品质钢管的性能;探讨了承受轴向应变钢管的进一步开发。     

A 5 V only one-transistor 256 K EEPROM with page-mode erase

Erasing and programming are achieved in the device through electron tunneling. In order to inhibit the programming to unselected cells, the unselected bit lines and word lines are applied with program-inhibiting voltages. The number of parity bits for error checking and correction (ECC) is fiver per 2 bytes, which are controlled by the lower byte (LB) signal. Using a conventional 1.5 μm design rule n-well CMOS process with a single metal layer and two polysilicon layers, the memory cell size is 7×8 μm² and the chip size is 5.55×7.05 mm². The chip size is reduced to 70% of a full-featured electrically erasable programmable ROM (EEPROM) with on-chip ECC     

120-ns 128 K*8-bit/64 K*16-bit CMOS EEPROMs

A 1-Mbit CMOS full-featured EEPROM using a 1.0- mu m triple-polysilicon and double-metal process is described. The design is aimed at developing a manufacturable 120-ns 1-Mbit EEPROM with small chip size. Therefore, an advanced memory cell with high read current, an improved differential sensing technique, and an efficient ECC scheme are developed. The differential sensing amplifier utilizes the output of a current sensing amplifier connected to unselected memory as a reference level. The cell size is 3.8*8 mu m/sup 2/ and the chip size is 7.73*11.83 mm/sup 2/. The device is organized as either 128 K*8 or 64 K*16 by via-hole mask options. A 256-byte/128-word page-mode programming is implemented.<>     

Analysis of coupling noise between adjacent bit lines in megabitDRAMs

Different bit-line structures, bit-line materials, widths, spacings, and passivation materials were fabricated to analyze the effect of the coupling noise between adjacent bit lines in megabit DRAMs. Each component of total bit-line capacitance was measured to obtain the bit-line-to-bit-line capacitance and the other contributions to the total bit-line capacitance. Accelerated soft error tests were performed on each sample. The results suggest the existence of two types of noise effects. One is the READ-signal degradation just after the work-line rises. The other is the disturbance in sensing operation. The larger the ratio of the bit-line coupling capacitance to the other bit-line capacitance contributions the more serious both the noise effects are. These noise mechanisms can be explained by the charge conservation model and the simulation of sensing operation. A polycide bit-line structure is less susceptible to these noises than an Al bit line because its thickness and layer position