Hybrid ring coupler for W-band MMIC applications using MEMS technology

The hybrid ring coupler was designed and fabricated on a GaAs substrate using surface micromachining techniques, which adopted dielectric-supported air-gapped microstrip line (DAML) structure. The fabrication process of DAML is compatible with the standard monolithic microwave integrated circuit (MMIC) techniques, and the hybrid ring coupler can be simply integrated into a plane-structural MMIC. The fabricated hybrid ring coupler shows wideband characteristics of the coupling loss of 3.57 /spl plusmn/ 0.22dB and the transmission loss of 3.80 /spl plusmn/ 0.08dB across the measured frequency range of 85 to 105GHz. The isolation characteristics and output phase differences are -34dB and 180/spl plusmn/1/spl deg/, at 94GHz, respectively.     

Automatic Transformation of Membrane‐Type Electronic Devices into Complex 3D Structures via Extrusion Shear Printing and Thermal Relaxation of Acrylonitrile–Butadiene–Styrene Frameworks

This work demonstrates a means of automatic transformation from planar electronic devices to desirable 3D forms. The method uses a spatially designed thermoplastic framework created via extrusion shear printing of acrylonitrile–butadiene–styrene (ABS) on a stress‐free ABS film, which can be laminated to a membrane‐type electronic device layer. Thermal annealing above the glass transition temperature allows stress relaxation in the printed polymer chains, resulting in an overall shape transformation of the framework. In addition, the significant reduction in the Young's modulus and the ability of the polymer chains to reflow in the rubbery state release the stress concentration in the electronic device layer, which can be positioned outside the neutral mechanical plane. Electrical analyses and mechanical simulations of a membrane‐type Au electrode and indium gallium zinc oxide transistor arrays before and after transformation confirm the versatility of this method for developing 3D electronic devices based on planar forms.     

Short-circuit power driven gate sizing technique for reducing powerdissipation

One major challenge in low-power technology is how to reduce overall power dissipation of a given subsystem without impacting its performance. In this paper we present a technique that can be applied to the nonspeed-critical nets in a circuit in order to reduce overall power dissipation. This technique involves a study of short-circuit power dissipation as a function of input signal slews and output load conditions, to aid in making a judicious choice of drive strengths for various gates in a circuit. The resulting low-power solution does not degrade the original performance and yields a circuit which occupies less silicon area. The technique described here can be incorporated into any power optimization or synthesis tool. Lastly, we present the savings in power and area for a 32-b carry lookahead adder which was designed using the technique described here     

Improvement of TEOS-chemical mechanical polishing performance by control of slurry temperature

Effects of slurry temperature on the chemical mechanical polishing (CMP) performance of tetra-ethyl ortho-silicate (TEOS) film with silica and ceria slurries were investigated. The change of slurry properties as a function of different slurry temperatures was also studied to obtain higher removal rates and smoother surface morphology. The changes observed with increasing temperature are as follows: the pH showed a slight tendency to decrease, the conductivity of the slurry showed a tendency to increase, the particle size in the slurry decreased, and the zeta potential of the slurry decreased with temperature. The removal rates linearly increased and maintained at the temperature of about 40 °C. The hydroxyl (OH⁻) groups increased in the slurry as the slurry temperature increased and then they diffused into the TEOS film. The surface of the TEOS film became hydro-carbonated by the diffused hydroxyl groups. The hydro-carbonated surface of TEOS film could be removed more easily. Better surface morphology of TEOS films could be obtained at 40 °C of silica slurry and at 90 °C of ceria slurry. It is found that the CMP performance of TEOS film could be significantly improved or controlled by change of slurry temperature with the same slurry.     

Highly configurable capacitive interface circuit for tri‐axial MEMS microaccelerometer

A highly configurable capacitive interface circuit with on‐chip calibration capability for tri‐axial microaccelerometer is presented. The capacitive interface circuit is designed to be programmable, and can reduce the output errors due to the parasitic capacitance variations and process variations. The capacitive sensing chain adopts the chopper stabilisation, and includes the front‐end charge amplifier with three 10‐bit programmable capacitor arrays, 9‐bit digital‐to‐analogue converter and 10‐bit programmable gain amplifier. The calibration coefficients are stored to the on‐chip erasable programmable read only memory. The outputs from the three‐channel capacitive sensing chain are converted to digital signal by the integrated 14‐bit algorithmic analogue‐to‐digital converter. After calibrating the 48 samples, all the samples meet the desired specification range. Before the calibration, the errors of the average values of the output offset and gain were +47.1% and ?85.9%, respectively. After the calibration, however, the errors of the average values of the output offset and gain are reduced to be 0.3% and 0.5%, respectively. The resolutions for x/y‐axis and z‐axis are measured to be 326 and 728?µg, respectively.     

A physical and scalable I-V model in BSIM3v3 for analog/digitalcircuit simulation

A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation. Including the major physical effects in state-of-the art MOS devices, the model describes current characteristics from subthreshold to strong inversion as well as from the linear to the saturation operating regions with a single I-V expression, and guarantees the continuities of I_ds, conductances and their derivatives throughout all V_gs, V_ds, and T_bs, bias conditions. Compared with the previous BSIM models, the improved model continuity enhances the convergence property of the circuit simulators. Furthermore, the model accuracy has also been enhanced by including the dependencies of geometry and bias of parasitic series resistances, narrow width, bulk charge, and DIBL effects. The new model has the extensive built-in dependencies of important dimensional and processing parameters (e.g., channel length, width, gate oxide thickness, junction depth, substrate doping concentration, etc.). It allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling. The model has been implemented in the circuit simulators such as Spectre, Hspice, SmartSpice, Spice3e2, and so on     

Bit-level systolic arrays for modular multiplication

This paper presents bit-level cellular arrays implementing Blakley's algorithm for multiplication of twon-bit integers modulo anothern-bit integer. The semi-systolic version uses 3n(n+3) single-bit carry save adders and 2n copies of 3-bit carry look-ahead logic, and computes a pair of binary numbers (C, S) in 3n clock cycles such thatC+S[0, 2N). The carry look-ahead logic is used to estimate the sign of the partial product, which is needed during the reduction process. The final result in the correct range [0,N) can easily be obtained by computingC+S andC+S–N, and selecting the latter if it is positive; otherwise, the former is selected. We construct a localized process dependence graph of this algorithm, and introduce a systolic array containing 3nw simple adder cells. The latency of the systolic array is 6n+w–2, wherew=n/2. The systolic version does not require broadcast and can be used to efficiently compute several modular multiplications in a pipelined fashion, producing a result in every clock cycle.     

On the performance of adaptive Gram-Schmidt algorithm forinterference cancelling arrays

A detailed performance analysis of the least mean square (LMS) algorithm to update each stage of an adaptive Gram-Schmidt processor in interference cancelling adaptive arrays is presented. It is shown that although the number of adaptive weights in the processor is proportional to M². the total misadjustment contributed by weight jittering is proportional to only M, where M is the size of the processor. In absolute terms, the weight jittering noises do not accumulate as would be expected, but cancel one another out and decrease in magnitude as the optimal powers become smaller from one processing stage to the next. For optimal performance, the feedback factors used in the individual LMS loops should be normalized so that the amount of misadjustment contributed and the convergence time constant are the same for all processing stages. All the weights belonging to one processing stage must be adjusted in a synchronous manner with the same input vector. This synchronous updating requirement is essential for the cancellation of the jittering noises, although in situations where the weights are adaptively updated in a time-multiplexed manner, it may appear more efficient to update each weight based on the most current inputs     

Contribution of the fractal dimension to multiscale adaptive filtering of SAR imagery

Radar images can show great variability from pixel to pixel, which is an obstacle to effective processing. This variability, due to speckle created by the radar wave coherence, necessitates the use of more adapted filters. Previous studies have shown that multiresolution wavelet analysis yields better results but produces artefacts due to multiscale decomposition. This paper proposes a method that reduces these effects by introducing the fractal dimension. The resultant filter combines wavelet decomposition and variance change model based on the level of variance estimated by studying the fractal dimension of the image.     

A viable self-aligned bottom-gate MOS transistor technology for deep submicron 3-D SRAM

In this paper, the effect of the nonself-aligned process on the performance variation of a bottom-gate metal oxide semiconductor (MOS) transistor is discussed using a device simulator. The simulation results predict that the nonself-aligned bottom-gate MOS transistor cannot be scaled into the deep submicron regions. A simple fully self-aligned bottom-gate (FSABG) metal oxide semiconductor field effect transistor (MOSFET) technology is then proposed and developed. A new technique for forming thermal oxide on poly-Si serving as the bottom-gate dielectric is also investigated. It is found that the quality of the oxide on the poly-Si recrystallized by the metal induced uni-lateral crystallization (MIUC) is much higher than that by the solid phase crystallization (SPC). Deep submicron fully self-aligned bottom-gate pMOS transistors are fabricated successfully using the proposed technology. The experimentally measured results indicate the device performances depend strongly on the channel-width, and get comparable to that of a single crystal MOSFET if the channel width is less than 0.5/spl mu/m. The effects of the channel width on the device performances are discussed. In addition, the experimental results also confirm that the proposed technology has a good control of the channel film thickness.