A 32×32-bit multiplier using multiple-valued MOS current-modecircuits

A 32×32-bit multiplier using multiple-valued current-mode circuits has been fabricated in 2-μm CMOS technology. For the multiplier based on the radix-4 signed-digit number system, 32×32-bit two's complement multiplication can be performed with only three-stage signed-digit full adders using a binary-tree addition scheme. The chip contains about 23600 transistors and the effective multiplier size is about 3.2×5.2 mm², which is half that of the corresponding binary CMOS multiplier. The multiply time is less than 59 ns. The performance is considered comparable to that of the fastest binary multiplier reported     

First plasma experiment on spherical tokamak device UTST

The UTST (University of Tokyo Spherical Tokamak) device was constructed for the purpose of exploring the formation of ultrahigh‐beta ST (spherical tokamak) plasma using the double null plasma merging method. When two plasmas merge together to form a single plasma, magnetic field lines reconnect, and magnetic field energy is converted to plasma kinetic energy, increasing the plasma beta. Merging start‐up has been demonstrated in the TS‐3/4, START, and MAST devices using coils inside the vacuum vessel, and the TS‐3 plasma obtained a 50% beta. In order to demonstrate start‐up in a more reactor‐relevant situation, UTST has all poloidal field (PF) coils outside the vacuum vessel. The first plasma experiment on the UTST was begun in December 2007. In the results, the plasma obtained 10 kA by using only the outer PF coils and a single ST was generated in the lower area (z = –0.3 to –1.0 m) close to a washer gun. This result suggests that another washer gun on the top of the UTST can allow the generation of ST in the upper area and merging start‐up by using outer PF coils. © 2012 Wiley Periodicals, Inc. Electr Eng Jpn, 179(2): 20–26, 2012; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21216     

30 GHz pulse train generation from a multiquantum well electroabsorption intensity modulator

Stable optical pulse trains with repetition rates as high as 20-30 GHz have been successfully generated at 1.55 mu m from an InGaAs/InAlAs multiquantum well electroabsorption modulator for the first time.<>     

标准与专科池:使用专科许可领导市场

解释了为什么以利润为目的的公司参与标准化活动和特别关注标准与专利的关系,并从经济学角度,使用反公共的悲剧和跨越式发展的概念分析了这个问题.反公共的悲剧解释了为什么公司交叉授权他们的专利许可以及为什么标准化组织的专利政策包含交叉授权.跨越式发展解释了为什么拥有为实施标准的必要专利的公司将他们的专利许可授予没有相关专利的公司.通过向外授予专利许可,公司在短期内可以获得经济利益,在长期可以获得影响市场发展的战略机会,并为民营公司提供一些建议.     

Penetration and stainability of modified Sato's lead staining solution.

The penetration and stainability of modified Sato's lead staining solution containing calcined lead citrate were studied. Modified Sato's lead solution was preserved for 1 week and for 2 years, each at room temperature and at 4 degrees C. Specimens were stained with these solutions to measure the stainability. After 2-min staining, specimens were stained to the depth of 1.0-1.2 microns even when there had been 2-year preservation of the staining solution. This modified solution could be preserved for a long time and good penetration and stainability could still be obtained. This solution is also suitable for the observation of semithin sections.     

Budding of fowlpox and pigeonpox viruses at the surface of infected cells

Chick embryo fibroblasts and chorioallantoic membranes infected with fowlpox virus (FWPV) or pigeonpox virus (PPV) were examined by transmission and scanning electron microscopy. Immature virus particles were observed in finely granular areas, i.e. virus factories, of the cytoplasm. These particles had various forms depending on their stages of development. Many tubular structures were also seen in these regions. Mature virus particles with ellipsoidal or brick-shaped forms enclosing electron-dense cores were detected throughout the cytoplasm. Notably, there was a high frequency of virus budding at the cell surface, but only occasional virus wrapping in the cytoplasm. Another remarkable feature of the infected cells was accumulation of many virions just beneath the plasma membrane, indicating that this phenomenon is closely related to virus budding. Based on the observed frequency of budding, this mechanism seems to be the predominant way for FWPV and PPV to exit the cell.     

Design methodology of embedded DRAM with virtual-socketarchitecture

This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRAM control circuitry with the DRAM memory array is handled as a hardware macro, resulting in the increase in design TAT. On the other hand, our proposed architecture provides the DRAM control circuitry as a software macro to take advantage of the automated tools based on synchronous circuit design. With array-generator technology, this architecture can achieve high quality and quick turn-around time (QTAT) of flexible embedded DRAM that is almost the same as the CMOS ASIC. We applied this virtual-socket architecture to the development of the 61-Mb synchronous DRAM core using 0.18-μm design rule and confirmed the high-speed operation, 166 MHz at CAS latency of two, and 180 MHz at that of three. The experimental results show that our proposed architecture can be applied to the development of the high-performance embedded DRAM with design QTAT     

A multigigabit DRAM technology with 6F2 open-bitlinecell, distributed overdriven sensing, and stacked-flash fuse

A multigigabit DRAM technology was developed that features a low-noise 6F² open-bitline cell with fully utilized edge arrays, distributed overdriven sensing for operation below 1 V, and a highly reliable post-packaging repair scheme using a stacked-flash fuse. This technology, which can be used to fabricate a 0,13-μm 180-mm² 1-Gb DRAM assembled in a 400-mil package, was verified using a 57.6-mm², 200-MHz array-cycle, 256-Mb test chip with 0.109-μm² cells