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71.
72.
Kilchytska V. Neve A. Vancaillie L. Levacq D. Adriaensen S. van Meer H. De Meyer K. Raynaud C. Dehan M. Raskin J.-P. Flandre D. 《Electron Devices, IEEE Transactions on》2003,50(3):577-588
This work presents a systematic comparative study of the influence of various process options on the analog and RF properties of fully depleted (FD) silicon-on-insulator (SOI), partially depleted (PD) SOI, and bulk MOSFET's with gate lengths down to 0.08 /spl mu/m. We introduce the transconductance-over-drain current ratio and Early voltage as key figures of merits for the analog MOS performance and the gain and the transition and maximum frequencies for RF performances and link them to device engineering. Specifically, we investigate the effects of HALO implantation in FD, PD, and bulk devices, of film thickness in FD, of substrate doping in SOI, and of nonstandard channel engineering (i.e., asymmetric Graded-channel MOSFETs and gate-body contacted DTMOS). 相似文献
73.
A hybrid optical fibre amplifier is described that consists of a fluoride-based thulium-doped fibre amplifier and a silica-based erbium-doped fibre amplifier connected in a cascade. The amplifier has a gain of more than 25 dB and a noise figure of less than 9 dB over a wide wavelength region of 1458-1540 nm. 相似文献
74.
Static energy reduction techniques for microprocessor caches 总被引:1,自引:0,他引:1
Hanson H. Hrishikesh M.S. Agarwal V. Keckler S.W. Burger D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2003,11(3):303-313
Microprocessor performance has been improved by increasing the capacity of on-chip caches. However, the performance gain comes at the price of static energy consumption due to subthreshold leakage current in cache memory arrays. This paper compares three techniques for reducing static energy consumption in on-chip level-1 and level-2 caches. One technique employs low-leakage transistors in the memory cell. Another technique, power supply switching, can be used to turn off memory cells and discard their contents. A third alternative is dynamic threshold modulation, which places memory cells in a standby state that preserves cell contents. In our experiments, we explore the energy and performance tradeoffs of these techniques. We also investigate the sensitivity of microprocessor performance and energy consumption to additional cache latency caused by leakage-reduction techniques. 相似文献
75.
T. Choi J.‐H. Jang C.K. Ullal M.C. LeMieux V.V. Tsukruk E.L. Thomas 《Advanced functional materials》2006,16(10)
The probing of the micromechanical properties within a two‐dimensional polymer structure with sixfold symmetry fabricated via interference lithography reveals a nonuniform spatial distribution in the elastic modulus “imprinted” with an interference pattern in work reported by Tsukruk, Thomas, and co‐workers on p. 1324. The image prepared by M. Lemieux and T. Gorishnyy shows how the interference pattern is formed by three laser beams and is transferred to the solid polymer structure. The elastic and plastic properties within a two‐dimensional polymer (SU8) structure with sixfold symmetry fabricated via interference lithography are presented. There is a nonuniform spatial distribution in the elastic modulus, with a higher elastic modulus obtained for nodes (brightest regions in the laser interference pattern) and a lower elastic modulus for beams (darkest regions in the laser interference pattern) of the photopatterned films. We suggest that such a nonuniformity and unusual plastic behavior are related to the variable material properties “imprinted” by the interference pattern. 相似文献
76.
S. V. Doronin 《Chemical and Petroleum Engineering》2006,42(7-8):461-464
Current features are considered in the calculation of carrying capacities for constructions in engineering plant (EP). Methods
and algorithms are described for EP calculations with comprehensive incorporation of the effects from technological and working
defects on the behavior of structures under standard and emergency conditions.
__________
Translated from Khimicheskoe i Neftegazovoe Mashinostroenie, No. 8, pp. 38–40, August, 2006. 相似文献
77.
Suetsugu T. Kazimierczuk M.K. 《IEEE transactions on circuits and systems. I, Regular papers》2006,53(7):1468-1476
Design equations for satisfying the off-nominal operating condition [i.e., only the zero-voltage switching (ZVS) condition] of the Class-E amplifier with a linear shunt capacitance at a duty ratio D=0.5 are derived. A new parameter s (V/s), called the slope of switch voltage when the switch turns on is introduced to obtain an image of the distance from the nominal conditions. By examining off-nominal Class-E operation degree of the design freedom of the Class-E amplifier increases by one. In addition various amplifier parameters such as operating frequency, output power, and load resistance range can be set as design specifications. For example, the peak switch voltage and switch current can be taken into account in the design procedure. Examples of a design procedure of the Class-E amplifier for off-nominal operation are given. The theoretical results were verified with PSpice simulation and experiments. 相似文献
78.
Starting from a microscopic Hamiltonian defined on a semi-infinite cubic lattice, and employing a mean-field approximation, the surface parameters relevant for wetting in confined ternary mixtures are derived. These are found in terms of the microscopic coupling constants, and yield a physical interpretation of their origins. In comparison with the standard expression for the surface free-energy density, several new terms arising from the derivation are identified. The influence of the surface parameters on a predicted unbinding transition in a mixture of oil, water, and amphiphile demonstrate that existing results are robust to the addition of the extra surface terms. 相似文献
79.
Takauchi H. Tamura H. Matsubara S. Kibune M. Doi Y. Chiba T. Anbutsu H. Yamaguchi H. Mori T. Takatsu M. Gotoh K. Sakai T. Yamamura T. 《Solid-State Circuits, IEEE Journal of》2003,38(12):2094-2100
We describe a CMOS multichannel transceiver that transmits and receives 10 Gb/s per channel over balanced copper media. The transceiver consists of two identical 10-Gb/s modules. Each module operates off a single 1.2-V supply and has a single 5-GHz phase-locked loop to supply a reference clock to two transmitter (Tx) channels and two receiver (Rx) channels. To track the input-signal phase, the Rx channel has a clock recovery unit (CRU), which uses a phase-interpolator-based timing generator and digital loop filter. The CRU can adjust the recovered clock phase with a resolution of 1.56 ps. Two sets of two-channel transceiver units were fabricated in 0.11-/spl mu/m CMOS on a single test chip. The transceiver unit size was 1.6 mm /spl times/ 2.6 mm. The Rx sensitivity was 120-mVp-p differential with a 70-ps phase margin for a common-mode voltage ranging from 0.6 to 1.0 V. The evaluated jitter tolerance curve met the OC-192 specification. 相似文献
80.
V. N. Pavlechko 《Journal of Engineering Physics and Thermophysics》2004,77(1):115-120
Relations for determining a motive force in a complex model of mass transfer as applied to concurrent, countercurrent, and cross motion of the vapor and liquid phases have been introduced. These forces have been compared for different forms of organization of the flow, and their comparison with similar quantities from the known Murphree and Hausen models is presented. 相似文献