Low-Power VLSI Implementation of the Inner Receiver for OFDM-Based WLAN Systems

In this paper, we propose low-power designs for the synchronizer and channel estimator units of the Inner Receiver in wireless local area network systems. The objective of the work is the optimization, with respect to power, area, and latency, of both the signal processing algorithms themselves and their implementation. Novel circuit design strategies have been employed to realize optimal hardware and power efficient architectures for the fast Fourier transform, arc tangent computation unit, numerically controlled oscillator, and the decimation filters. The use of multiple clock domains and clock gating reduces the power consumption further. These blocks have been integrated into an experimental digital baseband processor for the IEEE 802.11a standard implemented in the 0.25mum- 5-metal layer BiCMOS technology from Institute for High Performance Microelectronics.     

Diagnosis and Consulting for Control Network Performance Engineering of CSMA-Based Networks

Network performance engineering can verify the design and dimensioning of large-scale control networks like CSMA-based building automation networks. It combines performance analysis with diagnosis methods to evaluate the network utilization and to detect design errors before installation and can therewith save the expenses of overdimensioning and redesign. This paper will develop a diagnosis model based on fault trees that is able to use the huge amount of performance analysis results to identify design errors and analyze their coherences. This enables not only a fast tracing back of fault causes and the derivation of solutions; it can also visualize the fault coherence to the user and help him to understand his design. Additional consulting tools implement best practice strategies, to support the user in parameterization.     

A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC

A 0.9 V third-order double-sampled delta-sigma audio ADC is presented. A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. A three-level quantizer with simple dynamic element matching was used to improve linearity. The prototype IC implemented in a 0.13 CMOS process achieves 92 dB DR, 91 dB SNR and 89 dB SNDR in a 24 kHz audio signal bandwidth, while consuming 1.5 mW from a 0.9 V supply. The prototype operates from 0.65 V to 1.5 V supply with minimal performance degradation.     

An Adaptive Recipe Implementation in Case‐Based Formalism for Abnormal Condition Management

This paper deals with accurate recipe implementation for abnormal condition management in a batch process using a case‐based reasoning (CBR) approach. A set of new problems can be solved by reusing proven process solutions. The proposed system integrates quantitative and qualitative parameters for adaptation of cases. A novel methodology to generate accurate recipes and to adapt to the processes is introduced during normal and abnormal conditions. In particular, the differences between current conditions and the references (recipes) should be managed to prevent any hazardous conditions arising. The processes are evaluated using their similarity to the past cases. This intelligent approach distinguishes plausible cases, generates accurate recipes, and adapts to new situations. The aim is to use the offline historical process data and safety related information in order to propose changes and adjustments in the processes.     

Selective Transport of Bismuth Ions through Supported Liquid Membrane

A new supported liquid membrane (SLM) system was prepared for the selective transport of bismuth ions from the aqueous feed into the aqueous permeate phase. The support of the SLM was a thin porous polypropylene or polyvinylidene fluoride membrane impregnated with diisooctyldithiophosphinic acid (Cyanex 301) as mobile carrier in 4‐chloroacetophenon as organic solvent. Cyanex 301 acts as a highly selective carrier for the uphill transport of bismuth ions through the SLM. In the presence of HNO₃ as a metal ion acceptor in the strip solution, the transport of bismuth ions into the strip side reached 70 % of the initial feed concentration after 3.5 hours. The selectivity and efficiency of bismuth transport from aqueous solutions containing different mixtures of cations were investigated. In the presence of P₂O₇^2– ions as suitable masking agent in the feed solution, the interfering effects of other cations were completely eliminated. The selective transport of bismuth through SLM is superior to liquid‐liquid extraction or through bulk liquid membranes. This is due to the high efficiency. The SLM reduces the solvent requirements, combines extraction and stripping operations in a single process and allows the use of highly selective extractants. The system may be applied to samples containing very low bismuth concentrations.     

Poly(Styrene‐Divinylbenzene) Based Media for Liquid Chromatography

The latest developments and in particular important synthetic aspects for the preparation of modern poly(styrene‐divinylbenzene) (PS‐DVB) based liquid chromatography (LC) supports are reviewed. In this context, the chemistry of particular porous and nonporous, functionalized, monolithic, coated silica and more specialized mixed organic PS‐DVB media is covered. Special consideration is given to modern approaches such as micro‐(μ)‐HPLC and coating techniques and their most important applications. Synthetic particularities relevant to the corresponding applications are outlined.     

Implementing total quality management at the U.S. Department of Defense

This paper examines Total Quality Management (TQM) as defined by Dr. W. Edwards Deming including Deming's fourteen points and explains how the United States' Department of Defense (DOD) defines TQM and why TQM is necessary. It also covers how the DOD is planning on implementing TQM and the policy that has been established as guidance in the implementation process.     

A fine-grain architecture for relational database aggregationoperations

The design and simulation of a bit-sliced processor for relational database aggregation functions, are discussed. The processor, which addresses an important, computationally expensive problem in database computers, takes two tuples as input (one bit at a time) and returns two bits as output every clock cycle. A larger aggregation unit uses a number of identical slice processors, connected according to odd-even network topology, to achieve improved performance on a parallel pipelined processor. The data processing time is completely overlapped with the input and output of data to and from the unit. The design is independent of the tuple size, and since a bit-serial computation is used, the system requires limited interconnection