Kinetically Accelerating Elementary Steps via Bridged Ru-H State for the Hydrogen-Evolution in Anion-Exchange Membrane Electrolyzer

Designing hydrogen evolution reaction (HER) electrocatalysts for facilitating its sluggish adsorption kinetics is crucial in generating green hydrogen via sustainable water electrolysis. Herein, a high-performance ultra-low Ruthenium (Ru) catalyst is developed consisting of atomically-layered Ru nanoclusters with adjacent single Ru sites, which executs a bridging-Ru-H activation strategy to kinetically accelerate the HER elementary steps. Owing to its optimal electronic structure and unique adsorption configuration, the hybrid Ru catalyst simultaneously displayed a drastically reduced overpotential of 16 mV at 10 mA cm⁻² as well as a low Tafel slope of 35.2 mV dec⁻¹ in alkaline electrolyte. When further coupled with a commercial IrO₂ anode catalyst, the ensembled anion-exchange membrane water electrolyzer achievs a current density of 1.0 A cm⁻² at a voltage of only 1.70 V_cell. In situ spectroscopic analysis verified that Ru single atom and atomically-layered Ru nanoclusters in the hybrid materials play a critical role in facilitating water dissociation and weakening *H adsorption, respectively. Theoretical calculations further elucidate the underlaying mechanism, suggesting that the dissociated proton at the single atom Ru site orients itself adjacently with Ru nanoclusters in a bridged structure through targeted charge transfer, thus promoting Volmer-Heyrovsky dynamics and boosting the HER activity.     

Chiral Se Nanobrooms with Wavelength and Polarization Sensitive Scattering

High-index dielectric nanostructures offer strong magnetic and electric resonances in the visible range and low optical losses, stimulating research interest in their use for light manipulation technologies. Lithographic fabrication of dielectric nanostructures, while providing precise control over the pattern dimensions, limits the scalability of this approach for practical applications due to an inefficient fabrication process and limited production quantity. Here, the colloidal synthesis of high-index chiral dielectric nanostructures with a broom-like geometry made from trigonal Se is demonstrated. The anisotropic morphology and crystal structure of Se nanobrooms enable both linearly and circularly polarized scattering, as well as spectrum variation along the particle axis, which is, to the authors’ knowledge, the first observation of such behavior from dielectric colloidal nanostructures. To show the versatility of the highly scattering Se NB suspensions, 2D and 3D printing of Se NB inks are demonstrated as a proof of concept. This approach provides a way to manipulate light using aqueous dispersions of high-index dielectric nanostructures, unlocking their potential to fit in various morphologies and dimensions in 2D and 3D for broad applications.     

Thermosensitive Molecular,Colloidal, and Bulk Interactions Using a Simple Surfactant

Efficient use of (nano)particle self‐assembly for creating nanostructured materials requires sensitive control over the interactions between building blocks. Here, a very simple method for rendering the interactions between almost any hydrophobic nano‐ and microparticles thermoswitchable is described and this attraction is characterized using colloid probe atomic force microscopy (CP‐AFM). In a single‐step synthesis, a thermoresponsive surfactant is prepared that through physical adsorption generates a thermosensitive brush on hydrophobic surfaces. These surface layers can reversibly trigger gelation and crystallization of nano‐ and microparticles, and at the same time can be used to destabilize emulsions on demand. The method requires no chemical surface modification yet is universal, reproducible, and fully reversible.     

下一代测试系统化解闪存复杂性问题

随着移动电话和掌上计算机等个人电子设备需求的驱动,闪存器件已经通过快速发展,迈上了更高的容量和性能水平.今天,半导体制造厂商发现,对更为先进的闪存产品的需求与日俱增,其交付方式或为独立的闪存器件,或者作为拥有逻辑电路的内核,嵌入单芯片器件中,或与微控器、逻辑或静态内存共同出现在芯片中.对闪存制造商来说,要想在这些高度竞争的市场中取得成功,就要求它们能够严格控制测试成本,尽管器件本身正日趋复杂.由于闪存在大小尺寸、速度和复杂性方面都在不断增加,制造商正在寻求更为成本有效的单次插入测试解决方案,并希望其能够解决目前正在浮现的测试挑战.随着新测试技术的出现,制造商可以运用成本经济的下一代测试平台有效解决日益严峻的闪存复杂性问题.     

Analytical comparison of sensor signal processing enhancements forNDT synthetic aperture ultrasonic imaging

The results of a detailed analytical study of the effects of sensor processing techniques on clutter suppression and image enhancement for nondestructive testing (NDT) systems are presented. A relatively simple beamforming/diffraction model is developed for near-field, wideband, synthetic aperture ultrasonic imaging in NDT systems. The physical model is used to quantitatively evaluate a variety of front-end sensor signal processing tradeoffs for the enhanced detection and sizing of defects. It is shown using statistical microscopic scattering calculations that a combination of increased spatial sampling and rectangular windowing can increase the signal-to-clutter ratio by ~10 dB while maintaining crack size resolutions well below future projected specifications. The sensor signal processing image enhancements are demonstrated by the construction of simulated strip-map SAFT (synthetic aperture focusing technique) images of metallic crack defects in the presence of large numbers of randomly distributed clutter (simulated grain boundary) scatterers.     

HIST: A hierarchical self test methodology for chips,boards, and systems

This article presents the HIST approach, which allows the automated insertion of self test hardware into hierarchically designed circuits and systems to implement the RUNBIST instruction of the IEEE 1149.1 standard. To achieve an optimal and throughout self testable system, the inherent design hierarchy is fully exploited. All chips and boards are provided with appropriate test controllers at each hierarchy level. The approach is able to detect all those faults, which are in the scope of the underlying self test algorithms. In this paper the hierarchical test architecture, the test controllers as well as all necessary synthesis procedures are presented. Finally a successful application of the HIST approach to a cryptography processor is described.     

Elastic and plastic contributions to X-ray Line broadening of InGaAsP/InP Heterostructures

The coherency state of MOCVD grown InGaAsP/InP double-heterostructure wafers was examined and their effects on the structural properties were determined in this study. Lattice mismatches were measured using {511} asymmetric and (400) symmetric x-ray reflections. The chemical lattice misfit and the elastic strain were also calculated. Misfit dislocations were examined by both x-ray topography and photoluminescence imaging. The x-ray full width at half maximum (FWHM) varied with the degree of mismatch. The largest FWHM was obtained for samples containing the misfit dislocations. It was found that FWHM is influenced not only by the plastic deformation, but also by the elastic strain. To model the dependence of the FWHM, the radius of curvature was measured, and its contribution to the x-ray line broadening was calculated. Also, the contribution from misfit dislocations was taken into account. This model assumes that the dislocations are planar and interact weakly with each other. Good agreement between measured and calculated values was obtained. Thus, it is concluded that the major contribution to x-ray line broadening ofelastically strained sample is the lattice curvature induced by misfit strain, and that the dominant factor affecting x-ray FWHM ofplastically deformed sample is lattice relaxation induced by misfit dislocation.     

A 0.9-V microcontroller for portable applications

A 0.9-1.6-V, 1-MHz, 8-b microcontroller based on the 68HC08 architecture is presented. In addition to standard digital microcontroller functions, the chip features RAM, ROM, phase-locked loop (PLL) clock synthesis, and liquid crystal displays (LCD) drive capabilities operating from the voltage supply range of a single AA or AAA battery. The design used a library of CMOS microcontroller building blocks, converted into a low-voltage technology using unilateral transistors. The design approach was to optimize the conversion strategy for each functional block and to provide new designs when the conversion was insufficient. The chip exceeded specifications with blocks showing full functionality down to 0.7 V     

A 533-MHz BiCMOS superscalar RISC microprocessor

This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm×10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5-μm BiCMOS process and requires 3.6 and 2.1 V power supplies     

A Test Methodology for High Performance MCMs

Satellite and avionics applications represent an ideal application for the tremendous performance, cost, space, andreliability benefits of MCMs. These advantages are only realized,however, if accompanied by an efficient test strategy whichverifies defect-free fabrication. This paper describes a methodology developed to test high performance VLSI CMOS ICs thathave been mounted onto a multi-chip silicon substrate. A teststrategy, which addresses testing from the wafer level through tothe populated substrate, is detailed. This strategy uses acombination of LSSD, AC LSSD-On-Chip Self Test, Deterministic Delay Fault Testing, and Design for Partitionability to ensure high testquality at a reasonable cost. The methodology is then contrastedto alternative approaches.