A 146-mm/sup 2/ 8-gb multi-level NAND flash memory with 70-nm CMOS technology

An 8-Gb multi-level NAND Flash memory with 4-level programmed cells has been developed successfully. The cost-effective small chip has been fabricated in 70-nm CMOS technology. To decrease the chip size, a one-sided pad arrangement with compacted core architecture and a block address expansion scheme without block redundancy replacement have been introduced. With these methods, the chip size has been reduced to 146 mm/sup 2/, which is 4.9% smaller than the conventional chip. In terms of performance, the program throughput reaches 6 MB/s at 4-KB page operation, which is significantly faster than previously reported and very competitive with binary Flash memories. This high performance has been achieved by the combination of the multi-level cell (MLC) programming with write caches and with the program voltage compensation technique for neighboring select transistors. The read throughput reaches 60 MB/s using 16I/O configuration.     

Thickness scaling limitation factors of ONO interpoly dielectricfor nonvolatile memory devices

This paper describes the scaling limitation factors of ONO interpoly dielectric thickness, mainly considering the charge retention capability and threshold voltage stability for nonvolatile memory cell transistors with a stacked-gate structure, based on experimental results. For good intrinsic charge retention capability, either the top- or bottom-oxide thickness should be greater than around 6 nm. On the other hand, a thicker top oxide structure is preferable to minimize degradation due to defects. It has been confirmed that a 3.2 nm bottom-oxide shows detectable threshold voltage instability, but 4 nm does not. Effective oxide thickness scaling down to around 13 nm should be possible for flash memory devices with a quarter-micron design rule     

An image analyzing system using an artificial neural network forevaluating the parenchymal echo pattern of cirrhotic liver and chronichepatitis

To objectively evaluate the parenchymal echo pattern of cirrhotic liver and chronic hepatitis, the authors applied an image analyzing system (IAS) using a neural network. Autopsy specimens in a water tank (n=13) were used to examine the relationship between the diameter of the regenerative nodule and the coarse score (CS) calculated by IAS. CS was significantly correlated with the diameter of the regenerative nodule (p<0.0001, r=0.966). CS is considered to be useful for evaluating the coarseness of the parenchymal echo pattern     

Polarization-controlled single-mode VCSEL

Relative intensity noise (RIN) in a vertical-cavity surface-emitting laser (VCSEL) was greatly reduced through the use of polarization control to eliminate competition between two orthogonal polarization states by ensuring there was only one polarization state. Polarization was stable with optical feedback of up to 10%. Polarization control was achieved by inducing a small loss anisotropy in fundamental transversal mode VCSEL's. Anisotropic post structures, such as a rectangular post, an oblique post, or a zigzag-sidewall post, were found to be effective in creating loss anisotropy without serious degradation of other VCSEL characteristics such as light-output power or beam profile     

Effect of catch cup geometry on 3D boundary layer flow over the wafer surface in a spin coating

Recently, development of high technology has been required for the formation of thin uniform film in manufacturing processes of semiconductor as the semiconductor instruments become more sophisticated. Spin coating is usually used for spreading photoresist on a wafer surface. However, since rotating speed of the disk is very high in spin coating, the dropped photoresist scarers outward and reattaches on the film surface. A catch cup is set up outside the wafer in spin coating, and scattered photoresist mist is removed from the wafer edge by the exhaust flow generated at the gap between the wafer edge and the catch cup. In the dry process of a spin coating, it is a serious concern that the film thickness increases near the wafer edge in the case of low rotating speed. The purpose of this study is to make clear the effect of the catch cup geometry on the 3D boundary layer flow over the wafer surface and the drying rate of liquid film.     

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

A 4-Mb high-speed DRAM (HSDRAM) has been developed and fabricated by using 0.7-μm L_eff CMOS technology with PMOS arrays inside n-type wells and p-type substrate plate trench cells. The 13.18-mm×6.38-mm chip, organized as either 512 K word×8 b or 1 M word×4 b, achieves a nominal random-access time of 14 ns and a nominal column-access time of 7 ns, with a 3.6-V V_cc and provision of address multiplexing. The high level of performance is achieved by using a short-signal-path architecture with center bonding pads and a pulsed sensing scheme with a limited bit-line swing. A fast word-line boosting scheme and a two-stage word-line delay monitor provide fast word-line transition and detection. A new data output circuit, which interfaces a 3.6-V V_cc to a 5-V bus with an NMOS-only driver, also contributes to the fast access speed by means of a preconditioning scheme and boosting scheme. Limiting the bit-line voltage swing for bit-line sensing results in a low power dissipation of 300 mW for a 60-ns cycle time     

Design of pseudo-ternary and quaternary alloys by superlattices consisting of (zn,cd)(s,se) binary ii–vi compounds

Theoretical design of pseudo-ternary and quaternary alloys by superlattice structures consisting of (Zn,Cd)(S,Se) binary II–VI compounds has been studied. For pseudo-ternary ZnCdS and ZnCdSe alloys, the superlattices with two layers in a cycle, i.e., ZnS/CdS and ZnSe/CdSe are considered, and for pseudo-quaternary ZnCdSSe alloy, the two superlattice structures with more than two layers in a cycle are considered. In order to design and evaluate these superlattices, the expression for the equilibrium in-plane lattice constant of these superlattices has been derived by minimizing the total elastic strain energy in the cycle. The combinations of layer thicknesses in a cycle and the effective bandgap of these superlattices have been calculated while the elastic strain effect was included. The usefulness of these superlattice structures has been evaluated.     

Dye-sensitized solar cell made of mesoporous titania by surfactant-assisted templating method

Nanocrystalline mesoporous titania was obtained by surfactant-assisted templating method using tetraisopropyl orthotitanate modified with acethylacetone and laurylamine hydrochloride as template. This material was applied for the electrode of dye-sensitized solar cell. The mesoporous TiO₂ (MP-TiO₂) cells exhibited higher short-circuit photocurrent density and solar energy conversion efficiency compared to P25 (a typical commercial titania powder) cells. The incident photon to current conversion efficiency spectrum of MP-TiO₂ can be improved by using the cell made with 5% P25 additive. Double-layer titania cells were fabricated to further improve cell performance by increasing the film thickness and light scattering. The solar conversion efficiency up to 8.06% was obtained by using the double-layer titania cell sintered at 450 °C for 2 h.     

Thick Film Patterned Ceramics Using UV-Curable Pastes

Screen-printed layers of Al₂O₃, BaTiO₃, 0.90Pb(Mg_1/3Nb_2/3)-0₃–0.10PbTiO₃, Pb(Zr,Ti)O₃, ZnO, and glass alumina pastes have been patterned using photoprinting techniques. Curability of each paste by ultraviolet light and formation of holes with various diameters were studied for application as a production method for very small-sized vias. The dependence of hole diameters on various experimental parameters is presented and discussed. Wall slopes were found to depend on the transmission of the powders used in the pastes.     

Piezoresistivity in Polymer-Ceramic Composites

Composite materials composed of randomly dispersed semiconducting ceramic particles in an insulating polymer matrix show a pronounced change in resistivity with pressure. Different amounts of iron oxide (Fe₃O₄) powder and antimony-doped tin oxide (SnO₂:Sb) powder were dispersed in an epoxy polymer matrix to form pressure-sensitive composites. In each family of materials, an insulator-to-semiconductor transition is observed in agreement with percolation theory. Composites within a certain range of filler content showed substantial piezoresistive effect under both uniaxial and hydrostatic pressure in which sensitivity is controlled by the choice of filler material and the volume fraction. The effect of temperature on the piezoresistance effect was also examined. Piezoresistors made from Fe₃O₄ composites showed larger temperature changes than those filled with Sb-doped SnO₂.