Temperature-compensation circuit techniques for high-density CMOSDRAMs

Temperature-compensation circuit techniques are presented for the CMOS DRAM internal voltage converter, the RC-delay circuit, and the back-bias generator, which do not need any additional process steps. The above-mentioned circuits have been designed and evaluated through a 16-Mb CMOS DRAM process. These circuits have shown an internal voltage converter (IVC) with an internal voltage temperature coefficient of 185 ppm/°C, and an RC-delay circuit with a delay time temperature coefficient of 0.03%/°C. As a result, a 6.5-ns faster RAS access time and improved latchup immunity have been achieved, compared with conventional circuit techniques     

An adaptive algorithm for separating and tracking multipledirectional sources in linear arrays

An algorithm for spatially filtering out, enhancing, and tracking individual directional sources in an adaptive array is proposed and investigated. In this algorithm, the sources are separated by using an adaptive beamformer whose outputs are processed by using the LMS algorithm to track distinct sources individually. From the LMS weights used, the source locations can be estimated. Whenever significant changes in these are detected, the beamformer is updated so that its outputs will be due to different sources in the steady state. With this algorithm, the problems of look-direction errors in look-direction constrained arrays and of large signal power in power inversion arrays are eliminated, and the enhancement of multiple moving sources becomes a natural process. Furthermore, because the sources are individually tracked and the beamformer is only updated occasionally, the algorithm possesses fast tracking behavior, and its implementation complexity is comparable to that of beamformer-based adaptive arrays using the LMS algorithm     

Optimization of Si NC/P3HT Hybrid Solar Cells

Silicon nanocrystals (Si NCs) are shown to be an electron acceptor in hybrid solar cells combining Si NCs with poly(3‐hexylthiophene) (P3HT). The effects of annealing and different metal electrodes on Si NC/P3HT hybrid solar cells are studied in this paper. After annealing at 150 °C, Si NC/P3HT solar cells exhibit power conversion efficiencies as high as 1.47%. The hole mobility in the P3HT phase extracted from space‐charge‐limited current measurements of hole‐only devices increases from 2.48 × 10^?10 to 1.11 × 10^?9 m² V^?1 s^?1 after annealing, resulting in better transport in the solar cells. A quenching of the open‐circuit voltage and short‐circuit current is observed when high work function metals are deposited as the cathode on Si NC/P3HT hybrid devices.     

Electrical characteristics of nMOSFETs fabricated on hybrid orientation substrate with amorphization/templated recrystallization method

The use of hybrid orientation technology (HOT) with direct silicon bond (DSB) wafers consisting of a (1 1 0) crystal orientation layer bonded to a bulk (1 0 0) handle wafer provides promising opportunities for easier migration of bulk CMOS designs to higher performance materials. However, the material quality of nMOSFETs regions, which has been undergone amorphization/templated recrystallization (ATR) process for transforming the Si surface into (1 0 0) orientation, is still a concern because the ATR-induced defects (i.e., dislocation loops or threads) at the recrystallization layer, could degrade gate oxide integrity. In this paper, we report an investigation of charge pumping and low-frequency (1/f) noise in HOT nMOSFETs. Devices with the increased anneal time brought out a significant reduction in the charge pumping current and 1/f noise, which indicates ATR-induced defects were suppressed and consequently the “low-trap-density” of the Si/SiO₂ interface. Finally, for the first time, the behavior of 1/f noise for HOT nMOSFETs was investigated, and could be described by a unified model, i.e. a combination of carrier-number fluctuations and mobility fluctuations.     

Thickness dependent gate oxide quality of thin thermal oxide grownon high temperature formed SiGe

For thin oxides grown on high temperature formed Si_0.3Ge_0.7, the gate oxide quality is strongly dependent on oxide thickness and improves as thickness reduces from 50 to 30 Å. The thinner 30 Å oxide has excellent quality as evidenced by the comparable leakage current, breakdown voltage, interface-trap density and charge-to-breakdown with conventional thermal oxide grown on Si. The achieved good oxide quality is due to the high temperature formed Si_0.3Ge_0.7 that is strain relaxed and stable during oxidation. The possible reason for strong thickness dependence may be due to the lower GeO₂ content formed in thinner 30 Å oxide rather than strain relaxation related rough surface or defects     

Selection of network and learning parameters for an adaptive neural robotic control scheme

This paper presents the results of a study in the design of a neural network based adaptive robotic control scheme. The neural network used here is a two hidden layer feedforward network and the learning scheme is the well-known backpropagation algorithm. The neural network essentially provides the inverse of the plant and acts in conjunction with a standard PD controller in the feedback loop. The objective of the controller is to accurately control the end position of a single link manipulator in the presence of large payload variations, variations in the link length and also variations in the damping constant. Based on results of this study, guidelines are presented in selecting the number of neurons in the hidden layers and also the parameters for the learning scheme used for training the network. Results also indicate that increasing the number of neurons in the hidden layer will improve the convergence speed of learning scheme up to a certain limit beyond which the addition of neurons will cause oscillations and instability. Guidelines for selecting the proper learning rate, momentum and fast backpropagation constant that ensure stability and convergence are presented. Also, a relationship between the r.m.s. error and the number of iterations used in training the neural network is established.     

Hall and drift mobilities in molecular beam epitaxial grown GaAs

A series of nominally undoped and Si-doped GaAs samples have been grown by molecular beam epitaxy (MBE) with Hall concentrations ranging from 10¹⁵ to 10¹⁹ cm⁻³ and mobilities measured at 77 and 300K by Hall-van der Pauw methods. Drift mobilities were calculated using the variational principle method and Hall scattering factors obtained from a relaxation-time approximation to permit cross-correlation of experimental data with drift or Hall mobilities and actual or Hall electron concentrations. At 77K, both high purity and heavily doped samples are well represented by either drift or Hall values since piezoelectric acoustic phonon scattering and strongly screened ionized impurity scattering hold the Hall factor close to unity in the respective regimes. Between n≊10¹⁵ and 10¹⁷ cm⁻³, where lightly screened ionized impority scattering predominates, Hall mobility overestimates drift mobility by up to 50 percent and Hall concentration similarly underestimates n. At 300K, polar optical phonons limit mobility and a Hall factor up to 1.4 is found in the lowest doped material, falling close to unity above about 10¹⁶ cm⁻³. Our calculation also agrees remarkably well with the Hall mobility of the highest purity MBE grown sample reported to date.     

Variable VCC design techniques forbattery-operated DRAMs

Wide-voltage-range DRAMs with extended data retention are desirable for battery-operated or portable computers and consumer devices. The techniques required to obtain wide operation, functionality, and performance of standard DRAMs from 1.8 V (two NiCd or alkaline batteries) to 3.6 V (upper end of LVTTL standard) are described. Specific techniques shown are: (1) a low-power and low-voltage reference generator for detecting V_CC level; (2) compensation of DC generators, V_BB and V_PP, for obtaining high speed at reduced voltages; (3) a static word-line driver and latch-isolation sense amplifier for reducing operating current; and (4) a programmable V_CC variable self-refresh scheme for obtaining maximum data retention time over a full operating range. A sub-50-ns access time is obtained for a 16 M DRAM (2 M×8) by simulation