Survey of Deep-Learning Techniques in Big-Data Analytics

Big-data research studies relying upon Deep-learning methods are revitalized the decision-making mechanism in the business sectors and the enterprise domains. The firms’ operational parameters also have the dependency of the Big-data analytics phase, their way of managing the data, and to evolve the outcomes of Big-data implementation by using the Deep-learning algorithms. Deep-learning approaches enhancements in Big-data applications facilitate the decision-making process such as the information-processing to the employees, analytical potentials augmentation, and in the transition of more innovative work. In this DL-approach, the robust-patterns of the data-predictions resulted from the unstructured information by conceptualizing the Decision-making methods. Hence this paper reviewed the impact of the Deep-learning process utilizing the Big-data in the enterprise and Business sectors. Also this study provides a comprehensive survey of all the Deep-learning techniques illustrating the efficiency of Big-Data processing and their impacts of operational parameters. Further it concentrating the data-dimensionality factors and the Big-data complications rectifying by utilizing the DL-algorithms, usage of Machine-learning or deep-learning process for the decision-making mechanism in the Enterprise sectors and business sectors. This research discussed the predictions of the Big-data analytics resulting to the decision parameters within the organisations, and in the management of larger scale of datasets in Big-data analytics processing by utilizing the Deep-learning implementations. The comparative analysis of the reviewed studies has also been described by comparing existing approaches of Deep-learning methodologies in employing Big-data analytics.

     

Optical backbone and control of attocell network

Photonic Network Communications - For serving futuristic applications like distributed robotic systems with robots equipped with humanoid intelligence, wireless access to high-performance computing...     

A circularly polarized printed elliptical wide-slot antenna with high bandwidth-dimension-ratio for wireless applications

Wireless Networks - This paper outlines a simple design of a compact wideband microstrip-line fed antenna having two rotated elliptical wide-slots (EWSs). Here, both the elliptical wide-slots are...     

Inline frequency-non-degenerate phase-sensitive fibre parametric amplifier for fibre-optic communication

Error-free transmission of 2.5 Gbit/s data over 60 km of dispersion-compensated standard single-mode fibre is demonstrated by using an inline phase-sensitive fibre-parametric amplifier and double-sideband data modulation format. The power penalty for the phase-sensitive amplifier was found to be <0.5 dB compared to back-to-back for bit-error-rate >10/sup -6/ and <2 dB compared to that for an equivalent phase-insensitive fibre-parametric amplifier of the same gain.     

The design and evaluation of an end-to-end handoff management protocol

We introduce an efficient protocol for end-to-end handoff management in heterogeneous wireless IP-based networks. The protocol is based on the stream control transmission protocol (SCTP), and employs a soft-handoff mechanism that uses end-to-end semantics for signaling handoffs and for transmitting control messages. The design goal of this protocol is twofold—first, to reduce the home registration delay, and, second, to eliminate the tunnelling cost which exists in current proposals, such as Mobile IP and its derivatives. Furthermore, we propose successive enhancements to the initial mobility management framework for achieving better scalability. We present strong analytical and simulation-based results that show performance improvements over existing approaches. Antonios Argyriou is a Ph.D. candidate in the school of electrical and computer engineering, Georgia Institute of Technology. He received his M.S. degree from the Georgia Institute of Technology in 2003, and the diploma from Democritus University of Thrace in 2001, both in electrical and computer engineering. His research interests spawn in all aspects of computer networking while specific interests include wireless networks and multimedia communications. He is a student member of IEEE and ACM. Vijay Madisetti is a professor of electrical and computer engineering at the Georgia Institute of Technology. He splits his time among teaching, research and entrepreneurship. His interests are design, prototyping, and packaging of electronic systems, virtual prototyping, embedded software systems, and computer networks. He obtained his Ph.D. in electrical engineering and computer science from the University of California at Berkeley. He is a member of the IEEE and the Computer Society.     

Significance of image representation for face verification

In this paper we discuss the significance of representation of images for face verification. We consider three different representations, namely, edge gradient, edge orientation and potential field derived from the edge gradient. These representations are examined in the context of face verification using a specific type of correlation filter, called the minimum average correlation energy (MACE) filter. The different representations are derived using one-dimensional (1-D) processing of image. The 1-D processing provides multiple partial evidences for a given face image, one evidence for each direction of the 1-D processing. Separate MACE filters are used for deriving each partial evidence. We propose a method to combine the partial evidences obtained for each representation using an auto-associative neural network (AANN) model, to arrive at a decision for face verification. Results show that the performance of the system using potential field representation is better than that using the edge gradient representation or the edge orientation representation. Also, the potential field representation derived from the edge gradient is observed to be less sensitive to variation in illumination compared to the gray level representation of images.     

An Index-Based Location Management Scheme for PCS Network

Location management provides the guarantee to deliver a call to mobile user during the mobility of user and it is a key challenge in wireless cellular networks. In this paper, we are introducing a new index-based location management scheme. It is based on indexing of location update information at the home agent of network. A tuple of index will keep track of range of location update information and corresponding thread of it, connected to stack of information table. To register a new mobile user, the mobile switching centre will generate a new identification number with the help of mobile switching centre identification number and temporary mobile subscriber identity of subscriber. If, the identification number is with in the range of index then, the Care of Address of mobile subscriber is added to information table else, the index will be reconstruct based on new range of identification number. It has been observed that in proposed technique, the call setup delay and network overheads is reduces over the limitation of minor increment of registration delay. The analytical model and numerical result represents the effectiveness of proposed scheme over the existing schemes.     

Distributed Optimal Self-Organization in Ad Hoc Wireless Sensor Networks

This work is motivated by the idea of using randomly deployed wireless networks of miniature smart sensors to serve as distributed instrumentation. In such applications, often the objective of the sensor network is to repeatedly compute and, if required, deliver to an observer some result based on the values measured at the sensors. We argue that in such applications it is important for the sensors to self-organize in a way that optimizes network throughput. We identify and discuss two main problems of optimal self-organization: (1) building an optimal topology, and (2) tuning network access parameters, such as the transmission attempt rate. We consider a simple random access model for sensor networks and formulate these problems as optimization problems. We then present centralized as well as distributed algorithms for solving them. Results show that the performance improvement is substantial and implementation of such optimal self-organization techniques may be worth the additional complexity.     

Body Bias Voltage Computations for Process and Temperature Compensation

With continued scaling into the sub-90-nm regime, the role of process, voltage, and temperature (PVT) variations on the performance of VLSI circuits has become extremely important. These variations can cause the delay and the leakage of the chip to vary significantly from their expected values, thereby affecting the yield. Circuit designers have proposed the use of threshold voltage modulation techniques to pull back the chip to the nominal operational region. One such scheme, known as adaptive body bias (ABB), has become extremely effective in ensuring optimal performance or leakage savings. Our work provides a means to efficiently compute the body bias voltages required for ensuring high performance operation in gigascale systems. We provide a computer-aided design (CAD) perspective for determining the exact amount of bias voltages that can compensate both temperature and process variations. Mathematical models for delay and leakage based on minimal tester measurements are built, and a nonlinear optimization problem is formulated to ensure highest frequency operation under all conditions, and thereby minimize the overall circuit leakage. Three different algorithms are presented and their accuracies and runtimes are compared. The algorithms have been applied to a wide range of process and temperature corners, for a 65- and 45-nm technology node-based process. A suitable implementation mechanism has also been outlined.     

Compact Surface Potential Model for FD SOI MOSFET Considering Substrate Depletion Region

In this paper, by solving the 1-D Poisson equation using appropriate boundary conditions, we report a closed-form surface potential solution for all the three surfaces (gate oxide-silicon film interface, silicon-film-buried oxide interface, and buried oxide-substrate interface) of fully depleted silicon-on-insulator (SOI) MOSFETs by considering the effect of substrate charge explicitly. During the model derivation, it is assumed that the silicon film is always fully depleted and the back silicon film surface is never inverted. The calculated values of the surface potentials obtained from the proposed model agree well with the iterative solution of exact Poisson equation with a maximum relative error bound of 0.3%. In the entire model, only two square roots, one exponential, and two logarithm terms are used and the continuity and differentiability of the resultant surface potential solutions are ensured making the proposed model computationally efficient.