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51.
This note proposes a simple linear matrix inequality (LMI) system for the design of static precompensators to reduce the interactions of a multivariable system. The approach is based on minimizing the H2 norm of a modified system and the LMIs are derived from the well known technique of pseudodiagonalisation. The approach is applied to two complex real-life benchmark problems with high levels of interaction. It is shown that its performance is significantly better than previously proposed LMI optimization techniques for designing static precompensators 相似文献
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太原精神病院污水处理系统改建为中水处理系统的工程设计 总被引:1,自引:0,他引:1
太原精神病医院将现有生活污水处理系统改建为中水回用系统,平均日处理水量100 m3.工程设计充分考虑了对原有设施的利用,生物处理单元采用生物接触氧化法.为减少污水提升次数,调节池设在生物处理单元之后.通过延长水力停留时间缓解水量、水质波动对沉淀、生物处理单元的不利影响,投入运行后效果良好. 相似文献
58.
The toughness of 31Mn2SiRE wear-resistance cast steel were increased by means of RE compound modification and high temperature austenitizing. The results show that the microstructures can be refined, needle and network ferrite are eliminated, the dislocation density and the quantity of dislocated martensite are increased remarkably, and the shape and distribution of inclusions are improved by the addition of RE. Therefore, the mechanical properties of the modified steel can be greatly increased, especially the toughness (αK) by 44%, yield strength (σs) by 10%, and elongation (δ5) by 42%. 相似文献
59.
We extend the definition of the classical Jacobi polynomials withindexes α, β>−1 to allow α and/or β to be negative integers. We show that the generalized Jacobi polynomials, with indexes corresponding to the number of boundary conditions in a given partial differential equation, are the natural basis functions for the spectral approximation of this partial differential equation. Moreover, the use of generalized Jacobi polynomials leads to much simplified analysis, more precise error estimates and well conditioned algorithms.Mathematics subject classification 1991. 65N35, 65N22, 65F05, 35J05 相似文献
60.
High-performance and power-efficient CMOS comparators 总被引:1,自引:0,他引:1
Chung-Hsun Huang Jinn-Shyan Wang 《Solid-State Circuits, IEEE Journal of》2003,38(2):254-262
Several design techniques for high-performance and power-efficient CMOS comparators are proposed. First, the comparator is based on the priority-encoding (PE) algorithm, and the dynamic circuit technique developed specifically for the priority encoder can be applied. Second, the PE function and the subsequent logic functions are merged and efficiently realized in the multiple output domino logic (MODL) to result in a shortened logic depth. The circuit in MODL CMOS is also compact and power efficient because few transistors are needed. Third, the multilevel look-ahead technique is used to shorten the path of priority-token propagation. Finally, the circuit is realized with a latch-based two-stage pipelined structure, and the comparison function is partitioned into two parts, with each part executed in each half of the clock cycle in a delay-balanced manner. Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators. Measurement results of the test chip conform with simulation results and prove the feasibility of the proposed techniques. 相似文献