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61.
62.
The major steps of sewerage rehabilitation include inspection of sewerage, assessment of structural conditions, computation of structural condition grades, and determination of rehabilitation methods and materials. Conventionally, sewerage rehabilitation planning relies on experts with professional background that is tedious and time-consuming. This paper proposes an automation model of planning optimal sewerage rehabilitation strategies for the sewer system by integrating image process, clustering technology, optimization, and visualization display. Firstly, image processing techniques, such as wavelet transformation and co-occurrence features extraction, were employed to extract various characteristics of structural failures from CCTV inspection images. Secondly, a classification neural network was established to automatically interpret the structural conditions by comparing the extracted features with the typical failures in a databank. Then, to achieve optimal rehabilitation efficiency, a genetic algorithm was used to determine appropriate rehabilitation methods and substitution materials for the pipe sections with a risk of mal-function and even collapse. Finally, the result from the automation model can be visualized in a geographic information system in which essential information of the sewer system and sewerage rehabilitation plans are graphically displayed. For demonstration, the automation model of optimal sewerage rehabilitation planning was applied to a sewer system in east Taichung, Chinese Taiwan. 相似文献
63.
64.
Design of two-level system stabilizers is considered using an optimal reduced-order model whose state variables are torque angles and speeds. The reduced-order model retains their physical meaning and is used to design a two-level linear feedback controller that takes into account the realities and constraints of the electrical power systems. The two-level control strategy is used, and a global control signal is generated from the output variables to minimize the effect of interaction. The effectiveness of this controller is evaluated, and an example, the multimachine system, is given to illustrate the advantages of the proposed method. The responses of the system with the two-level scheme and optimal reduced order scheme are included for comparative analyses 相似文献
65.
66.
The relatively fast diffusion of Au atoms in eutectic PbSn matrix is considered one of the contributing factors to the Au
embrittlement problem. In this study, we further investigated the Au embrittlement problem in high-Sn solders. Experimentally,
Sn3.5Ag (wt.%) spheres with 500-μm diameter were soldered over the Au/Ni soldering pads. It was found that some of the AuSn4 needles that formed after reflow inside the solder migrated back to the solder/pad interface during thermal aging. However,
the migration kinetics in high-Sn solders was slower compared to that in eutectic PbSn. The difference in migration kinetics
of AuSn4 in eutectic PbSn and SnAg was ascribed to the difference in the magnitudes of the Au flux and the Ni flux. In eutectic PbSn,
the Au flux was much greater than that of the Ni flux, and the Au and Ni flux were in the same order of magnitude in eutectic
SnAg. The relative magnitude of the Au and Ni flux changed in eutectic PbSn and SnAg because the homologous temperatures of
PbSn and SnAg were different. 相似文献
67.
69.
《石油沥青纸胎油毡》国家标准进行了第三次修订。本文介绍了修订的理由、修订的内容与依据,并与国内外同类产品标准进行了比较。 相似文献
70.
A Single-Die 124 dB Stereo Audio Delta-Sigma ADC With 111 dB THD 总被引:1,自引:0,他引:1
This paper presents a highly power-efficient stereo delta-sigma ADC designed for high-precision applications, with measured inter-channel isolation over 130 dB. This design adopts a single-loop, fifth-order, 33 level analog modulator with positive and negative feedforward paths. An interpolated multilevel quantizer with unevenly weighted quantization levels replaces a conventional 5-bit flash type quantizer. These new techniques suppress signal dependent energy inside the delta-sigma loop, reduce internal channel coupling and power consumption. Manufactured in 0.35 mum double poly, three metal CMOS process, the single-die chip includes two analog modulators, on-chip bandgap reference circuit, decimation filter and serial interface circuits. The core die area is around 14.8 mm2. The ADC achieves 124 dB dynamic range (A-weighted), -111 dB THD over 20 kHz bandwidth. Total power consumption is less than 330 mW. 相似文献