分层循环调度算法初探

在综合现有的一些算法的基础上,提出了一种分层循环(LRR)的调度算法.LRR调度算法采用了两次循环调度,不仅能提供保证速率的服务,而且能提供区分类型的服务,对不同类型的流提供不同的迟延特性,在一定程度上能避免低迟延队列的迟延范围的扩大.     

MOCVD实现InGaAsP波导对接生长的研究

采用低压MOCVD技术,通过对接界面和对接工艺的优化,获得了高质量的InGaAsP材料构成的对接波导,测量得到的对接波导光学损耗为7cm-1,说明该技术可以用来制作高质量的光电子集成器件.     

契比雪夫加权应用被动合成孔径处理算法研究

提出了将契比雪夫加权应用于被动合成孔径处理算法。被动合成孔径技术对小孔径基阵沿直线运动接收到的信号进行合成处理,从而达到虚拟大孔径基阵方位分辨力效果。将契比雪夫加权应用于线阵合成孔径前后波束图的指向性研究,对主瓣宽度变化予以合理解释。理论分析结合仿真验证表明,被动合成孔径处理算法应用契比雪夫加权可以在给定的旁瓣高度要求下获得等旁瓣级,等旁瓣级下可提高对弱目标信号的检测分辨能力。     

Development of Metallic Hermetic Sealing for MEMS Packaging for Harsh Environment Applications

Hermetic sealing of microelectromechanical system sensors is indispensable to ensure their reliable operation and also to provide protection during fabrication. This work proposes two prospective candidates for hermetic sealing for rugged environment applications, i.e., Al-Ge and Pt-In. Al-Ge was chosen due to its compatibility with complementary metal–oxide–semiconductor technology. Pt-In possesses the highest remelting temperature among all the solder systems, which is desired for high-temperature applications in both the energy and aerospace industries. The various bonding parameters for Al-Ge eutectic bonding and Pt-In transient liquid-phase (TLP) bonding have been optimized, and their influence on the bond quality is reported. Optimization of bonding parameters has been carried out with the objective of ensuring void-free bonds. A new configuration for stacking Al-Ge thin films has been demonstrated to tackle the issue of loss of Ge prior to bonding, since native Ge oxides are soluble in deionized water. The impact of solid-state aging prior to Al-Ge eutectic bonding has been investigated. The method of tailoring the phases in the Pt-In joint is also discussed. The prospects and constraints of eutectic and TLP bonding from the hermeticity perspective are discussed in detail. Furthermore, changes in the microstructure under aging at 300°C up to 500 h and the resulting influence on the mechanical properties are presented. The overall finding of this work is that Al-Ge can achieve better mechanical and hermetic performance for high-temperature applications.     

激光修调对CrSi薄膜电阻稳定性的影响

该文分析了激光修调对CrSi薄膜电阻稳定性的影响,获得了对CrSi薄膜电阻进行激光修调的优化方法.实验结果表明,150 ℃储存48 h,可完全消除激光修调带来的影响,使CrSi薄膜电阻温度系数降到了20×10-6/℃,提高了CrSi薄膜电阻网络的稳定性,从而为研制高性能模拟集成电路打下坚实的基础.     

具有阵列分布光束输出的TEA CO2激光器研究

通过对封离型外腔TEA CO2激光器谐振腔的腔元件参数的特殊选择,即选用两表面有夹角的未镀膜的Ge镜作为谐振腔的输出镜,得到阵列分布的激光束.绕腔轴旋转输出镜,在不同的角度可以得到不同的阵列输出光束.近场区域光斑尺寸内点阵数达7×16,光斑大小为26mm×17 mm,利用等厚干涉原理分析了这种光束的产生原因.     

Simulation and design methodology for a 50-Gb/s multiplexer/demultiplexer package

A 50 Gb/s package for SiGe BiCMOS 4:1 multiplexer and 1:4 demultiplexer targeting SONET OC-768 serial communication systems is introduced in this work. The package was designed to facilitate bit-error-rate tests and constructed with high-speed coaxial connectors, transmission lines on ceramic substrate, ribbon bonds for chip-to-package interconnects, and a metal composite housing. Numerical simulations were conducted to guide the package design, and both small signal measurements and operational tests were performed thereafter to verify the design and modeling concepts. To keep the model structure under the existing computing capability, the simulation was segmented into three sections - coaxial connector to transmission line, transmission line alone, and transmission line to ribbon bond, and then the results were assembled to predict the performance of the entire package. The package was operated up to 50 Gb/s with low degradation to input digital waveforms and free of error.     

多芯电缆屏蔽效能测试方法研究

首先介绍了屏蔽效能的定义,然后根据多芯电缆和同轴电缆的区别与联系,提出了适用于测量多芯屏蔽电缆效能的注入线测试方法,并且比较了测试结果和仿真结果,为测试人员合理选择有效的测试方法提供了依据。     

FDTD方法分析金属机箱的屏蔽特性

文中采用时域有限差分法对带孔缝机箱的屏蔽特性进行了仿真分析。比较了入射场极化方式不同的情况下机箱的屏蔽特征,得出的分析结论可用于指导机箱的电磁屏蔽设计和防护。     

A Model With Temperature-Dependent Exponent for Hot-Carrier Injection in High-Voltage nMOSFETs Involving Hot-Hole Injection and Dispersion

An improved hot-hole-involved interface-state generation model is proposed for hot-carrier injection (HCI) degradation in high-voltage (HV) nMOSFETs. This model is based on experiments over a wide range of temperatures, voltage conditions, simulation results, and the underlying physical mechanisms. The model provides a thorough picture of an HCI system in HV nMOSFETs, with hot-hole injection related to an additional maximum electric-field region. The hot-hole injection in HCI is assumed to introduce deeper localized hydrogen states in gate-oxide films than that in negative-bias temperature instabilities. This result facilitates the dispersive transport of hydrogen. Therefore, HCI degradation in HV transistors is explained within the framework of disorder-controlled hydrogen kinetics. The power-law model can successfully predict temperature dependences for HCI degradation.