Decision-directed maximum-likelihood estimation of OFDM framesynchronisation offset

The authors propose a method to estimate the synchronisation offset for orthogonal frequency division multiplexing (OFDM) frame alignment without resort to pilot tones. A decision-directed maximum-likelihood estimation of frame synchronisation offset is derived, and the performance of the proposed scheme is confirmed by computer simulation for QAM systems     

Modeling the I-V characteristics of fully depleted submicrometerSOI MOSFET's

In this paper, an analytic current-voltage model for submicrometer fully-depleted (FD) silicon-on-insulator (SOI) MOSFET's is presented. This model takes into account the source/drain series resistances which can be especially high in thin film SOI devices. The effect of drain induced conductivity enhancement is also included, which is important for submicrometer channels. The model is verified by comparison to measured SOI I-V characteristics. Good agreement is obtained for SOI film thicknesses ranging from 40 to 220 nm and effective channel lengths down to 0.25 μm     

Classification of pixels in a noisy grayscale image of polar ice

Often, in synthetic aperture radar (SAR) images of polar ice, one encounters shadow-like features across the images. Such features make it difficult to classify pixels into ice and water. Accordingly, it becomes a challenge to determine the true size and boundaries of ice floes in an SAR image of polar ice. We develop a simple statistical procedure which classifies pixels of an image by eliminating the effects of shadow-like features. Methodology developed in this paper is illustrated using some noisy SAR images of ice floes in the Arctic sea.     

A quadruple well, quadruple polysilicon BiCMOS process for fast 16Mb SRAM's

An advanced, high-performance, quadruple well, quadruple polysilicon BiCMOS technology has been developed for fast 16 Mb SRAM's. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts, achieves a cell area of 8.61 μm² with conventional I-line lithography and 7.32 μm² with I-line plus phase-shift or with deep UV lithography. The process features PELOX isolation to provide a 1.0 μm active pitch, MOSFET transistors designed for a 0.80 μm gate poly pitch, a double polysilicon bipolar transistor with aggressively scaled parasitics, and a thin-film polysilicon transistor to enhance bitcell stability. A quadruple-well structure improves soft error rate (SER) and allows simultaneous optimization of MOSFET and bipolar performance     

Physical model of drain conductance, gd, degradation ofNMOSFET's due to interface state generation by hot carrierinjection

Degradation of analog device parameters such as drain conductance, g_d, due to hot carrier injection has been modeled for NMOSFET's. In this modeling, mobility reduction caused by interface state generation by hot carrier injection and the gradual channel approximation were employed. It has been found that g_d degradation can be calculated from linear region transconductance, g_m, degradation which is usually monitored for hot carrier degradation of MOSFET's. The values of g_d degradation calculated from g_m degradation fit well to the measured values of g_d degradation The dependence of the g_d degradation lifetime on L_eff has been also studied, this model also provides an explanation of the dependence on L_eff. The model is then useful for lifetime predictions of analog circuits in which g_d degradation is usually more important than g_m degradation     

Effect of lanthanide ions on the phase behavior of dipalmitoylphosphatidylcholine multilamellar liposomes

The effect of lanthanide ions (Ln3+) and their coordination compounds of diethylenetriamine pentaacetic acid (DTPA) on the phase behavior of dipalmitoylphosphatidylcholine (DPPC) multi-lamellar liposomes has been studied by differential scanning calorimetry (DSC), Raman spectroscopy, and freeze-fracture electron microscopic techniques. The displacement of Ca2+ binding on DPPC liposomes by lanthanide ions was also studied. The results show that the binding degree of four kinds of chloride salts with DPPC liposomes is: YbCl3 > GdCl3 > LaCl3 > CaCl2. Lanthanide ions increase the phase transition temperature of DPPC liposomes and decrease the membrane fluidity. Freeze-fracture electron microscopic results show that La3+ enhances the order of DPPC membrane. The effect of coordination compounds of lanthanides with DTPA on the phase behavior of DPPC liposomes is smaller than that of their chlorides. La3+, Gd3+, and Yb3+, can displace Ca2+ binding on DPPC liposomes, but there coordination compounds of DTPA can hardly displace Ca2+. Raman spectroscopic results show that a very slight effect in lateral packing order of DPPC liposomes was observed at various concentrations of lanthanides.     

A new MMIC broadside coupler using an array of air-bridges for directivity enhancement

A new quadrature broadside coupler is proposed, which employs an array of air-bridges to enhance directivity via its phase-equalization effect on the c-mode and /spl pi/-modes. The realization of air-bridges follows a standard MMIC fabrication process. An experimental chip fabricated on the 75-/spl mu/m GaAs substrate verifies the air-bridge effect and shows wideband characteristics of the coupling of 3.2/spl plusmn/0.4 dB, the insertion loss of 3.9/spl plusmn/0.4 dB, the output phase deviation from quadrature less than 6/spl deg/, and the isolation greater than 18 dB from 20 to 40 GHz.     

Test data compression and test time reduction using an embedded microprocessor

Systems-on-a-chip (SOCs) with many complex intellectual property cores require a large volume of data for manufacturing test. The computing power of the embedded processor in a SOC can be used to test the cores within the chip boundary, reducing the test time and memory requirements. This paper discusses techniques that use the computing power of the embedded processor in a more sophisticated way. The processor can generate and reuse random numbers to construct test patterns and selectively apply only those patterns that contribute to the fault coverage, significantly reducing the pattern generation time, the total number of test applications and, hence, the test time. It can also apply deterministic test patterns that have been compressed using the characteristics of the random patterns as well as those of the deterministic patterns themselves, which leads to high compression of test data. We compare three fast run-length coding schemes which are easily implemented and effective for test-data compression. We also demonstrate the effectiveness of the proposed approach by applying it to some benchmark circuits and by comparing it with other available techniques.     

A One‐Kilobit PQR‐CMOS Smart Pixel Array

The photonic quantum ring (PQR) laser is a three dimensional whispering gallery (WG) mode laser and has anomalous quantum wire properties, such as microampere to nanoampere range threshold currents and √T‐dependent thermal red shifts. We observed uniform bottom emissions from a 1‐kb smart pixel chip of a 32×32 InGaAs PQR laser array flip‐chip bonded to a 0.35 µm CMOS‐based PQR laser driver. The PQR‐CMOS smart pixel array, now operating at 30 MHz, will be improved to the GHz frequency range through device and circuit optimization.