Tuning Interfacial Properties by Spontaneously Generated Organic Interlayers in Top‐Contact‐Structured Organic Transistors

Controlling the interfacial properties between the electrode and active layer in organic field‐effect transistors (OFETs) can significantly affect their contact properties, resulting in improvements in device performance. However, it is difficult to apply to top‐contact‐structured OFETs (one of the most useful device structures) because of serious damage to the organic active layer by exposing solvent. Here, a spontaneously controlled approach is explored for optimizing the interface between the top‐contacted source/drain electrode and the polymer active layer to improve the contact resistance (R_C). To achieve this goal, a small amount of interface‐functionalizing species is blended with the p‐type polymer semiconductor and functionalized at the interface region at once through a thermal process. The R_C values dramatically decrease after introduction of the interfacial functionalization to 15.9 kΩ cm, compared to the 113.4 kΩ cm for the pristine case. In addition, the average field‐effect mobilities of the OFET devices increase more than three times, to a maximum value of 0.25 cm² V^?1 s^?1 compared to the pristine case (0.041 cm² V^?1 s^?1), and the threshold voltages also converge to zero. This study overcomes all the shortcomings observed in the existing results related to controlling the interface of top‐contact OFETs by solving the discomfort of the interface optimization process.     

Dynamic exclusive-OR gate based on gate-induced Si islandsingle-electron transistor

Basic operation of a dynamic exclusive-OR gate implemented by a field effect transistor and a single-electron transistor is experimentally demonstrated, for the first time. Logic output voltage shows full swing operation at a supply voltage of 20 mV. Fabricated single-electron transistors are advantageous for implementing a multi-gate single-electron logic circuit     

A Signed Array Multiplier with Bypassing Logic

A low power digital signed array multiplier based on a 2-dimensional (2-D) bypassing technique is proposed in this work. When the horizontally (row) or the vertically (column) operand is zero, the corresponding bypassing cells skip redundant signal transitions to avoid unnecessary calculation to reduce power dissipation. An 8×8 signed multiplier using the 2-D bypassing technique is implemented on silicon using a standard 0.18 μm CMOS process to verify power reduction performance. The power-delay product of the proposed 8×8 signed array multiplier is measured to be 31.74 pJ at 166 MHz, which is significantly reduced in comparison with prior works.     

Energy-Efficient Double-Edge Triggered Flip-Flop

This paper presents a novel design for a double-edge triggered flip-flop (DETFF). A detailed analysis of the transistors used in the DETFF is carried out to determine the critical path. Therefore, the proposed DETFF employs low-V _th transistors at critical paths such that the power-delay product as well as the large area consumption caused by the low-V _th transistors can be resolved simultaneously. Therefore, the proposed DETFF fully utilizes the multi-V _th scheme provided by advanced CMOS processes without suffering from a large area penalty, slow clock frequency, and poor noise immunity. The proposed design is implemented using a typical 0.18-μm 1P6M CMOS process. The measurement results reveal that the proposed DETFF reduce the power-delay product by at lease 25% (i.e., dissipated energy).     

Direct Physical Imaging and Chemical Probing of LiFePO4 for Lithium‐Ion Batteries

The control of unexpectedly rapid Li intercalation reactions without structural instability in olivine‐type LiFePO₄ nanocrystals is one of the notable scientific advances and new findings attained in materials physics and chemistry during the past decade. A variety of scientific studies and technological investigations have been carried out with LiFePO₄ to elucidate the origins of many peculiar physical aspects as well as to develop more effective synthetic processing techniques for better electrochemical performances. Among the several features of LiFePO₄ that have attracted much interest, in this article we address four important issues—regarding doping of aliovalent cations, distribution of Fe‐rich secondary metallic phases, nanoparticle formation during crystallization, and antisite Li/Fe partitioning—by means of straightforward atomic‐scale imaging and chemical probing. The direct observations in the present study provide significant insight into alternative efficient approaches to obtain conductive LiFePO₄ nanocrystals with controlled defect structures.     

Facile Synthesis of Red/NIR AIE Luminogens with Simple Structures,Bright Emissions,and High Photostabilities,and Their Applications for Specific Imaging of Lipid Droplets and Image‐Guided Photodynamic Therapy

Red/near‐infrared (NIR) fluorescent molecules with aggregation‐induced emission (AIE) characteristics are of great interest in bioimaging and therapeutic applications. However, their complicated synthetic approaches remain the major barrier to implementing these applications. Herein, a one‐pot synthetic strategy to prepare a series of red/NIR‐emissive AIE luminogens (AIEgens) by fine‐tuning their molecular structures and substituents is reported. The obtained AIEgens possess simple structures, good solubilities, large Stokes shifts, and bright emissions, which enable their applications toward in vitro and in vivo imaging without any pre‐encapsulation or ‐modification steps. Excellent targeting specificities to lipid droplets (LDs), remarkable photostabilities, high brightness, and low working concentrations in cell imaging application make them remarkably impressive and superior to commercially available LD‐specific dyes. Interestingly, these AIEgens can efficiently generate reactive oxygen species upon visible light irradiation, endowing their effective application for photodynamic ablation of cancer cells. This study, thus, not only demonstrates a facile synthesis of red/NIR AIEgens for dual applications in simultaneous imaging and therapy, but also offers an ideal architecture for the construction of AIEgens with long emission wavelengths.     

Memory Access Optimized Implementation of Cyclic and Quasi-Cyclic LDPC Codes on a GPGPU

Software based decoding of low-density parity-check (LDPC) codes frequently takes very long time, thus the general purpose graphics processing units (GPGPUs) that support massively parallel processing can be very useful for speeding up the simulation. In LDPC decoding, the parity-check matrix H needs to be accessed at every node updating process, and the size of the matrix is often larger than that of GPU on-chip memory especially when the code length is long or the weight is high. In this work, the parity-check matrix of cyclic or quasi-cyclic (QC) LDPC codes is greatly compressed by exploiting the periodic property of the matrix. Also, vacant elements are eliminated from the sparse message arrays to utilize the coalesced access of global memory supported by GPGPUs. Regular projective geometry (PG) and irregular QC LDPC codes are used for sum-product algorithm based decoding with the GTX-285 NVIDIA graphics processing unit (GPU), and considerable speed-up results are obtained.     

Subjective Listening Experiments on a Front and Rear Array‐Based WFS System

Wave field synthesis (WFS) has been gathering more and more attention recently due to its ability to perfectly reproduce an original sound field. However, to realize theoretically perfect WFS, a four‐sided loudspeaker array that encloses the listener is required. However, it is difficult to build such a system except in large listening spaces, such as a theater or concert hall. In other words, if the listening space is a home, installing a side loudspeaker array is impractical. If the two side walls located to the left and right of the listener can be omitted, a setup using only front and rear loudspeaker arrays may be a solution. In this letter, we present a subjective listening experiment of sound localization/distance based on a WFS using a front and rear loudspeaker array system which is conducted on two listening points and shows average localization errors of 6.1° and 9.18°, while the average distance errors are –27% (0.5 m) and –29% (0.6 m), respectively.     

Effects of Interfacial Dielectric Layers on the Electrical Performance of Top‐Gate In‐Ga‐Zn‐Oxide Thin‐Film Transistors

We investigate the effects of interfacial dielectric layers (IDLs) on the electrical properties of top‐gate In‐Ga‐Zn‐oxide (IGZO) thin film transistors (TFTs) fabricated at low temperatures below 200°C, using a target composition of In:Ga:Zn = 2:1:2 (atomic ratio). Using four types of TFT structures combined with such dielectric materials as Si₃N₄ and Al₂O₃, the electrical properties are analyzed. After post‐annealing at 200°C for 1 hour in an O₂ ambient, the sub‐threshold swing is improved in all TFT types, which indicates a reduction of the interfacial trap sites. During negative‐bias stress tests on TFTs with a Si3N4 IDL, the degradation sources are closely related to unstable bond states, such as Si‐based broken bonds and hydrogen‐based bonds. From constant‐current stress tests of Id = 3 µA, an IGZO‐TFT with heat‐treated Si₃N₄ IDL shows a good stability performance, which is attributed to the compensation effect of the original charge‐injection and electron‐trapping behavior.