Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns     

An easy-to-use mismatch model for the MOS transistor

In this paper, a physics-based mismatch model is presented. It is demonstrated on a 0.18-/spl mu/m technology that a simple mismatch model can still be used to characterize deep-submicron technologies. The accuracy of the model is examined and found to be within 20% in the strong inversion region. Bulk bias dependence is modeled in a physical way. To extract the mismatch parameters, a weighted fit is introduced. It is shown that the width and length dependence of the mismatch parameters is given by the Pelgrom model.     

ESD–RF co-design methodology for the state of the art RF-CMOS blocks

This paper describes an approach to design ESD protection for integrated low noise amplifier (LNA) circuits used in narrowband transceiver front-ends. The RF constraints on the implementation of ESD protection devices are relaxed by co-designing the RF and the ESD blocks, considering them as one single circuit to optimise. The method is applied for the design of 0.25 μm CMOS LNA. Circuit protection levels higher than 3 kV HBM stress are achieved using conventional highly capacitive ggNMOS snapback devices. The methodology can be extended to other RF-CMOS circuits requiring ESD protection by merging the ESD devices in the functionality of the corresponding matching blocks.     

Origin of the threshold voltage instability in SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics

The magnitude of the V/sub T/ instability in conventional MOSFETs and MOS capacitors with SiO/sub 2//HfO/sub 2/ dual-layer gate dielectrics is shown to depend strongly on the details of the measurement sequence used. By applying time-resolved measurements (capacitance-time traces and charge-pumping measurements), it is demonstrated that this behavior is caused by the fast charging and discharging of preexisting defects near the SiO/sub 2//HfO/sub 2/ interface and in the bulk of the HfO/sub 2/ layer. Based on these results, a simple defect model is proposed that can explain the complex behavior of the V/sub T/ instability in terms of structural defects as follows. 1) A defect band in the HfO/sub 2/ layer is located in energy above the Si conduction band edge. 2) The defect band shifts rapidly in energy with respect to the Fermi level in the Si substrate as the gate bias is varied. 3) The rapid energy shifts allows for efficient charging and discharging of the defects near the SiO/sub 2//HfO/sub 2/ interface by tunneling.     

On the hot-carrier-induced post-stress interface trap generation inn-channel MOS transistors

A continued fast interface trap generation is observed in n-channel MOS transistors after termination of the hot-carrier stress. The magnitude of this post-stress effect is strongly dependent on the conditions of the preceding stress, on the post-stress conditions and on the process parameters. For measurements at 293 K, a simple model is proposed which is based on the release of hydrogen by the thermal detrapping of holes, and which can explain the observed dependencies. The importance of the post-stress D_it-generation is illustrated for the case of dynamic stress conditions where it can lead to an apparently deviating degradation behavior     

Nuclear cardiology, Part III: Scintigraphic evaluation of cardiac perfusion

OBJECTIVE: After reading Part III of this series of nuclear cardiology articles, the technologist should be able to: (a) compare and contrast radiopharmaceuticals used for myocardial perfusion imaging; (b) describe imaging protocols used for detecting coronary artery disease; and (c) describe imaging patterns seen following reconstruction of myocardial images.     

Modification of the porosity of pillared clays by carbon deposition. I. Polymer carbonization

In order to use pillared clays (PILC) for selective adsorption, further modifications of the porous structure are necessary. The deposition of carbon residues onto the porous structure of pillared clays by the carbonization of polymers (polyvinylalcohol) was proposed to achieve a controlled modification of the pore size. Ti and Al-pillared clays (calcined and non-calcined) were impregnated with PVA (different grades and different concentrations and subsequently carbonized to form carbon phases. The effect of the carbon deposits on the porosity of Ti- and Al-PILC is discussed in terms of pore-blocking, pore-filling and pore-narrowing. The deposition of carbon using PVA resulted in a complete pore-blocking for Al-PILC and in a narrowing of the pore size distribution for Ti-PILC, without achieving a controlled pore-narrowing.     

Local calibration of rigid pavement performance models using resampling methods

The performance prediction models in the Pavement-ME design software are nationally calibrated using in-service pavement material properties, pavement structure, climate and truck loadings, and performance data obtained from the Long-Term Pavement Performance programme. The nationally calibrated models may not perform well if the inputs and performance data used to calibrate those do not represent the local design and construction practices. Therefore, before implementing the new M-E design procedure, each state highway agency (SHA) should evaluate how well the nationally calibrated performance models predict the measured field performance. The local calibrations of the Pavement-ME performance models are recommended to improve the performance prediction capabilities to reflect the unique conditions and design practices. During the local calibration process, the traditional calibration techniques (split sampling) may not necessarily provide adequate results when limited number of pavement sections are available. Consequently, there is a need to employ statistical and resampling methodologies that are more efficient and robust for model calibrations given the data related challenges encountered by SHAs. The main objectives of the paper are to demonstrate the local calibration of rigid pavement performance models and compare the calibration results based on different resampling techniques. The bootstrap is a non-parametric and robust resampling technique for estimating standard errors and confidence intervals of a statistic. The main advantage of bootstrapping is that model parameters estimation is possible without making distribution assumptions. This paper presents the use of bootstrapping and jackknifing to locally calibrate the transverse cracking and IRI performance models for newly constructed and rehabilitated rigid pavements. The results of the calibration show that the standard error of estimate and bias are lower compared to the traditional sampling methods. In addition, the validation statistics are similar to that of the locally calibrated model, especially for the IRI model, which indicates robustness of the local model coefficients.     

Design rules for an integratable low-power amplifier/filter combination

In this paper design rules for a circuit topology in which there is an inseparable combination of an amplifier and a filter characteristic, are presented. By intentionally using the capacitance of an already present input sensor for the filtering, the total required integrated capacitance is much less than that in circuits, which have a separately designed amplifier and filter function. Consequently, it is possible to have the advantage of a better integratability. Moreover, less complexity in the design is achieved. The presented circuit shows a current-to-voltage conversion and an inherently controllable second-order low-pass filter characteristic. A discrete realization has been designed to test the circuit. This circuit operates down to a 1 V supply voltage and the transfer shows a 1.8 M currentto-voltage conversion with a bandwidth of 6 kHz. Measurement results of this circuit show that a 63 dB dynamic range can be achieved with a total required integrated capacitance of only 31 pF.