公司大门工程建设施工

大门小品建筑属多项目综合性工程。本文作者从管理者的角度 ,通过对公司大门及附属工程施工质量控制的总结 ,说明了质量控制应贯穿于工程施工的全过程     

Real-time measurement of pointing action by using DSP

This paper presents an approach of measuring in real-time the vector of finger that is pointing to an object. DSP is used in the operation processing unit in order to do the real-time processing. The steps include the extraction of flesh-colored regions from an image, the labeling of the flesh-colored regions, and the detection of two characteristic positions on the finger so that the direction that the finger is pointing at will be calculated. The entire process takes about 29 msec, which makes it possible to have the frame rate of 34 fps. With this frame rate, this measurement approach is considered real-time and promising to be merged into other application systems. This work was presented in part at the 13th International Symposium on Artificial Life and Robotics, Oita, Japan, January 31–February 2, 2008     

Optimal solutions for a dynamic bandwidth allocation scheme in high-speed networks

In this paper, we investigate the problem of determining the optimal bandwidth allocation for a Dynamic Bandwidth Allocation Scheme (DBAS). The objective is to minimize the total amount of bandwidth required to satisfy the Quality of Service (QoS) requirements of all traffic streams. It is shown that when the performance functions satisfy a certain number of conditions, there exists a unique optimal bandwidth allocation such that, for each traffic stream, either its QoS is just satisfied or its QoS is over-satisfied and it is allocated zero bandwidth. Such an allocation is said to be efficient. It is also shown that there exists a unique efficient allocation in the entire feasible region. An iterative algorithm is developed to compute the efficient allocation employing its special properties. Numerical examples are presented to demonstrate how the algorithm works. Future extensions of this work are also discussed.Partially supported by NSERC of Canada through grants OGP14020 and STRIN-200.     

Microfabricated liquid chromatography columns based on collocated monolith support structures

There is great interest today in massively parallel analytical strategies as a way to accelerate the rate of discovery in biological research; among them being 'biochips' and 'laboratories-on-a-chip'. The concept in the 'chip' approach is that minaturization will allow large numbers of operations to be performed in parallel in a small space, as in electronics. Proceeding with the semiconductor analogy, this paper demonstrates that in situ micromachining can be used to simultaneously fabricate millions of micrometer size, particle like structures in multiple liquid chromatography columns on a single wafer. Reduction of this widely used bioanalytical tool to the nanoliter volume, parallel processing, chip format is a significant step toward laboratories-on-a-chip.     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

Cost Effective VLSI Architectures for Full-Search Block-Matching Motion Estimation Algorithm

In this paper, we present efficient VLSI architectures for full-search block-matching motion estimation (BMME) algorithm. Given a search range, we partition it into sub-search arrays called tiles. By fully exploiting data dependency within a tile, efficient VLSI architectures can be obtained. Using the proposed VLSI architectures, all the block-matchings in a tile can be processed in parallel. All the tiles within a search range can be processed serially or concurrently depending on various requirements. With the consideration of processing speed, hardware cost, and I/O bandwidth, the optimal tile size for a specific video application is analyzed. By partitioning a search range into tiles with appropriate size, flexible VLSI designs with different throughput can be obtained. In this way, cost effective VLSI designs for a wide range of video applications, from H.261 to HDTV, can be achieved.     

Residual Stress Simulation of Injection Molding

In this study, distribution and history of residual stresses in plaque-like geometries are simulated based on linear thermoviscoelastic model, which helps to understand the mechanics and evolution of the residual stresses in the injection molding process. The numerical calculation of direction, combined with the specified boundary conditions. Results show that the stress variation across the thickness exhibits a high surface tensile value changing to a compressive peak value close to the surface, with the core region experiencing a parabolic tensile peak. Residual stress distribution throughout the thickness is almost same along the flowpath and the final residual stresses value near the gate is lower than the value near the end of flowpath.