Temperature compensated sapphire-rutile microwave whisperinggallery mode resonator

A 2 μm-thick film of rutile (TiO₂) was deposited on a sapphire disk using a sol-gel method to realise a temperature compensated microwave resonator operating in whispering gallery mode configuration. The resonator, though not yet completely optimised, shows turnover temperatures ranging from 40 to 60 K depending on the mode azimutal number. For the WGH_7,0,0 mode at 9.4 GHz, the Q-factor is of the order of 1.5×10⁶ at 46 K. The technique appears easy to implement and can be used for the design of a high-frequency stability microwave source     

Exploiting the on-chip inductance in high-speed clock distributionnetworks

On-chip inductance effects can be used to improve the performance of high-speed integrated circuits. Specifically, inductance improves the signal slew rate (the rise time), virtually eliminates short-circuit power consumption and reduces the area of the active devices and repeaters inserted to optimize the performance of long interconnects. These positive effects suggest the development of design strategies that benefit from on-chip inductance. An example of a clock distribution network is presented to illustrate the process in which inductance can be used to improve the performance of high-speed integrated circuits     

Methodology for studying the impact of intrinsic stress on thereliability of the electroless Ni UBM structure

A methodology for evaluating the reliability and the impact of intrinsic stresses on the electroless Ni under bump metallurgy (UBM) structure is presented. The first part of this work will address the testing methodology, which uses a pressure sensing device to determine the intrinsic stress in Ni due to the plating process. An optical method is used to capture deformation in the sensing device due to the Ni plating process. A finite element model is then used to calculate the intrinsic stress in the Ni film using the deformation output from the optical measurements. The second part of this work will address a predictive model used to determine the reliability of applying intrinsic stress values to a low cost electroless Ni UBM structure during the bump formation and solder reflow process. The combined work of the testing and predictive methodology provides a more effective and accurate method of predicting the Ni UBM reliability     

Effect of solder creep on the reliability of large area die attachment

High temperature solders have been widely used for power device die attachment. One typical solder is Pb92.5In5Ag2.5, which is a ternary eutectic alloy with a eutectic temperature of 310°C. Such a Pb-based solder has a low Young's modulus, a low yield strength, and a high strain prior to failure. So it can be used to attach large size silicon die to mismatched substrates. In this paper, stresses and strains have been studied on a large size power MOSFET attachment using the Pb92.5In5Ag2.5 solders. A commercial finite element analysis software is employed as the simulation tool. Three types of substrates, pure copper, copper–tungsten composite, and pure molybdenum are used in the study, where molybdenum has the closest coefficient of thermal expansion to silicon. In addition to the plastic deformation simulation of the solder, a creep model of the solder was incorporated due to the low melting temperature of the solder alloy. Firstly, stresses and strains are calculated during the cooling cycle after attachment. It is found that the creep strain is the dominant plastic strain at low cooling rate (10°C/min). Also, the maximum Von Mises stress in the Si chip is decreased from 174 to 62.7 MPa after adding creep strain. As expected, the maximum creep strain happens to the die-to-copper substrate attach. Simulation on temperature cycling is done from −55°C to +150°C. The peak Von Mises stress occurs at the low temperature extreme and holds steadily during the soaking period, indicating insignificant contribution from creep. The Von Mises stress at the high temperature extreme is much lower and decreases with holding time. Significant plastic deformation of the solder layer is observed in cooling cycles. For silicon to copper substrate attach, its plastic deformation increases with each cycle. For all three substrates used, considerable solder creep is observed at heating cycles. The creep strain is much larger than the rate-independent plastic strain in the solder alloy for all three types of substrates. It is concluded that solder creep is the dominant factor affecting long term reliability of power semiconductor die attachment.     

MBE-grown ZnSSe thin films on ITO substrates for liquid-crystal light valve applications

The MBE growth of ZnSSe alloy thin films on ITO substrates using ZnS and Se sources was studied and various structural and opto-electronic properties of the as-grown thin films were characterised. The XRD rocking curves resulting from these films indicate that the as-grown polycrystalline ZnSSe thin films have a preferred orientation along (1 1 1) direction. The evaluated crystal sizes as deduced from the FWHM of the XRD layer peaks were found to show a strong growth temperature dependence with the optimised temperature at about 290°C. TEM measurements done on these thin films also indicate a similar growth temperature dependence. The TEM cross-sectional micrograph of the sample grown at the optimised temperature shows a well-defined columnar structure whose nucleation seems to be highly correlated with the ITO grains. UV responsivity as high as 0.01 A/W and more than three orders of magnitude in rejection power for wavelengths longer than 450 nm have been achieved. It was also found that the sample grown at the optimised temperature has the lowest resistivity of 4.3×10¹¹ Ω cm, which provides a good match with that of a liquid-crystal layer. These results indicate that MBE-grown ZnSSe thin film is a promising candidate as the photoconductive material of liquid-crystal light valves for UV imaging applications.     

Growth-temperature-dependent optical and acetone detection properties of ZnO thin films

Zinc oxide (ZnO) thin films were prepared onto glass substrates at moderately low growth temperature by two-stage spray pyrolysis technique. The effects of growth temperature on structural, optical and acetone detection properties were investigated with X-ray diffractometry, a UV-visible spectrophotometer, photoluminescence (PL) spectroscopy and a homemade gas sensor testing unit, respectively. All the films are polycrystalline with a hexagonal wurtzite phase and exhibit a preferential orientation along [002] direction. The film crystallinity is gradually enhanced with an increase in growth temperature. The optical measurements show that all the films are physically highly transparent with a transmittance greater than 82% in the visible range. The band gap of the film is observed to exhibit a slight red shift with an increasing growth temperature. The PL studies on the films show UV/violet PL band at ～ 395 nm. Among all the films investigated, the film deposited at 250 ℃ demonstrates a maximum sensitivity of 13% towards 20 ppm of acetone vapors at 300 ℃ operating temperature.     

PSOBLAP: Particle Swarm Optimization-Based Bandwidth and Link Availability Prediction Algorithm for Multipath Routing in Mobile Ad Hoc Networks

Wireless Personal Communications - In mobile ad hoc network (MANET), optimal path identification is the main problem for implementing the Multipath routing technique. MANET desires an efficient...     

Tailoring the Optical Properties of Epitaxially Grown Biaxial ZnO/Ge,and Coaxial ZnO/Ge/ZnO and Ge/ZnO/Ge Heterostructures

Heterostructures of epitaxially grown biaxial ZnO/Ge, and coaxial ZnO/Ge/ZnO and Ge/ZnO/Ge heterostructured nanowires with ideal epitaxial interfaces between the semiconductor ZnO sublayer and the Ge sublayer have been fabricated via a two‐stage chemical vapor–solid process. Structural characterization by high‐resolution transmission electron microscopy and electron diffraction indicates that both the ZnO and Ge sublayers in the heterostructures are single crystalline. A good epitaxial relationship of (100)_ZnO∥(2 0)_Ge exists at the interface between ZnO and Ge in the ZnO/Ge biaxial heterostructure. There is also an epitaxial relationship of (0 0)_ZnO∥(020)_Ge at the interface between the ZnO and Ge substructures in the coaxial ZnO/Ge/ZnO heterostructures, and a good epitaxial relationship of (0 0)_ZnO∥(0 0)_Ge at the interface between ZnO and Ge in the Ge/ZnO/Ge coaxial heterostructure. Structural models for the crystallographic relationship between the wurtzite‐ZnO and diamond‐like cubic‐Ge subcomponents in the heterostructures are given. The optical properties for the synthesized heterostructures are studied by spatially resolved cathodoluminescence spectra at low temperature (20 K). Excitingly, the unique biaxial and coaxial heterostructures display unique new luminescence properties. It is concluded that the ideal epitaxial interface between ZnO and Ge in the prepared heterostructures induces new optical properties. The group II–VI Ge‐based nanometer‐scale heterostructures and their interesting optical properties may inspire great interest in exploring related epitaxial heterostructures and their potential applications in lasers, gas sensors, solar energy conversion, and nanodevices in the future.     

1.55 /spl mu/m bottom-emitting InAlGaAs VCSELs with Al/sub 2/O/sub 3//a-Si thin-film pairs as top mirror

A a 1.55 /spl mu/m InAlGaAs/InP vertical-cavity surface-emitting laser grown by metal-organic chemical vapour deposition is presented. Al/sub 2/O/sub 3//a-Si thin-film pairs and InAlGaAs/InAlAs epitaxial layers are used as a top mirror and a bottom-side output coupler, respectively. Direct modulation characteristics through singlemode fibre are reported at a speed of 2.5 Gbit/s.     

A wafer-level microcap array to enable high-yield microsystem packaging

Packaging represents a significant and expensive obstacle in commercializing microsystem technology (MST) devices such as microelectromechanical systems (MEMS), microopticalelectromechanical systems (MOEMS), microsensors, microactuators, and other micromachined devices. This paper describes a novel wafer-level protection method for MSTs which facilitate improved manufacturing throughput and automation in package assembly, wafer-level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized microcap array. This array consists of an assortment of small caps molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments associated with packaging. It may also include modifications which enhance its adhesion to the MST wafer or increase the MST device function. Depending on the application, the micromolded cap can be designed and modified to facilitate additional functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. The fabrication and materials selection of the microcap device is discussed in this paper. The results of wafer-level microcap packaging demonstrations are also presented.