To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6-μm N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage Vpp of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 μm×1.75 μm and 7.18 mm×17.39 mm, respectively 相似文献
A novel all-optical switching scheme in a reflective mode is proposed and its stable 60 Gbit/s operation at 1.307 mu m demonstrated. The scheme uses a 90 degrees polarisation rotation on reflection to compensate for birefringence phase turbulence in the Kerr media.<> 相似文献
A submillimeter (385–500 GHz) low-noise sideband-separating balanced SIS (Superconductor Insulator Superconductor) mixer (Balanced 2SB mixer) with high IRR (Image Rejection Ratio) has been successfully developed, whose SSB (Single SideBand) noise temperature is ~ 200 K (10hf/k) with an image rejection ratio of ≥?~10 dB. Balanced mixers have become a promising technology which would break through the limitation especially in terahertz receivers and heterodyne arrays. However, though there are examples in microwave with relatively worse noise performance, submillimeter and terahertz balanced mixers have rarely been developed in spite of their astronomical importance. The developed balanced 2SB mixer is not only the first one demonstrated at submillimeter frequency range, but also has very low noise, high IRR, wide detectable frequencies (385–500 GHz), and a flat IF output spectrum. The balanced 2SB mixer is composed of three RF hybrids, four DSB (Double SideBand) mixers, two 180° IF hybrids, and an IF quadrature hybrid. Several important performance indicators such as noise temperature, IRR, required LO (Local Oscillator) power, and IF spectra were measured. The measured LO power required for the balanced 2SB mixer was typically ~ 14 dB less than that of the single-ended mixers. 相似文献
A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-μm triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 μm2 , the smallest yet reported for 0.25-μm CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized 相似文献
We have developed a standing style transfer system, or "ABLE," for a person with disabled legs. It allows travel in a standing posture even on uneven ground, a standing up motion from a chair, and allows the stairs. ABLE consists of three modules: a pair of telescopic crutches, a powered lower extremity orthosis, and a pair of mobile platforms. We present here the conceptual design of ABLE and the motion of each module. Cooperative operations using the three modules are discussed through simulations. The standing up motion from a chair and ascending the stairs, however, have problems with adaptability to the environment and safety, because it executes the movement that has till now relied on telescopic crutches. To solve these problems, we propose a new motion technique and compare it with the previous one. In this paper, some experimental results are also presented. 相似文献
A high-speed wireline interfaces, e.g. LVDS (Low Voltage Differential Signaling), are widely used in the aerospace field for powerful computing in artificial satellites and aircraft [19]. This paper describes Bit Error Rate (BER) prediction methodology for wireline data transmission under irradiation environment at the design stage of data transmitter, which is useful in proactively determining if the design circuit meets the BER criteria of the target system. Using a custom-designed LVDS transmitter (TX) to enhance latch-up immunity [42], the relationship between transistor size and BER has been analyzed with focusing on Single Event Effect (SEE) as a cause of the bit error. The measurement was executed under 84Kr17+ exposure of 322.0 MeV at various flux condition from 1?×?103 to 5?×?105 count/cm2/sec using cyclotron facility. For the analysis of the bit error, circuit simulation by SPICE was utilized with expressing the irradiation environment by a current source model. The current source model represents a single event strike into the circuit at drain and substrate junctions in bulk MOSFETs. For the construction of the current source model, a charge collection was simulated at the single particle strike with the creation of 3D Technology CAD (TCAD) models for the MOS devices of bulk transistor process technology. The simulation result of the charge correction was converted to a simple time-domain equation, and the single-event current source model was produced using the equation. The single-event current source was applied to SPICE simulation at bias current related circuits in the LVDS transmitter, then simulation results are carefully verified whether the output data is disturbed enough to cause bit errors on wireline data transmission. By the simulation, sensitive MOSFETs have been specified and a sum of the gate area for these MOSFETs has 29% better correlation than the normal evaluation index (sum of the drain area) by comparison to the actual BER measurement. Through the precise revelation of the sensitive area by SPICE simulation using the current model, it became possible to estimate BER under irradiation environment at the pre-fabrication design stage.
This paper presents a new control scheme for a Class DE inverter, that is, frequency modulation/pulsewidth modulation (FM/PWM) control. Further, the FM/PWM controlled Class DE inverter is analyzed and we clarify performance characteristics. Since the FM/PWM controlled inverter has two control parameters, namely, the switching frequency and the switch-on duty ratio, it has one more degree of freedom for the control than the inverter with the conventional control scheme. The increased degree of freedom is used to minimize the switching losses. Therefore, it is possible to control the output power with high power-conversion efficiency for wide-range control. Carrying out the circuit experiments, we confirm that the experimental results agree well with the theoretical predictions quantitatively. For example, the proposed controlled inverter can control the output voltage from 56% to 191% of the optimum one, which is designed for 1.8 W at 1.0 MHz, with maintaining over 90% power-conversion efficiency. 相似文献
In this letter, we have simultaneously fabricated five wavelength-selectable microarray light sources (WSLs), each having a different wavelength range integrated with an electroabsorption (EA) modulator on a single wafer. We also introduced a novel device configuration scheme for wavelength-independent modulation. The five EA-WSLs fully covered the entire C-band and had a low uniform threshold current of 6 ± 1 mA at 25°C. Wavelength-independent extinction characteristics were obtained over a tuning wavelength range of 8 nm, and 2.5-Gb/s transmission over 600 km was successfully achieved 相似文献
An implementation of the IF section of WCDMA mobile transceivers with a set of two chips fabricated in an inexpensive 0.35-/spl mu/m two-poly three-metal CMOS process is presented. The transmit/receive chip set integrates quadrature modulators and demodulators, wide dynamic range automatic gain control (AGC) amplifiers, with linear-in-decibel gain control, and associated circuitry. This paper describes the problems encountered and the solutions envisaged to meet stringent specifications, with process and temperature variations, thus overcoming the limitations of CMOS devices, while operating at frequencies in the range of 100 MHz-1 GHz. Detailed measurement results corroborating successful application of the new techniques are reported. A receive AGC dynamic range of 73 dB with linearity error of less than /spl plusmn/2 dB and spread of less than 5 dB for a temperature range of -30/spl deg/C to +85/spl deg/C in the gain control characteristic has been measured. The modulator measurement shows a carrier suppression of 35 dB and sideband/third harmonic suppression of over 46 dB. The core die area of each chip is 1.5 mm/sup 2/. 相似文献
Long pulse operation up to 1 msec of a high frequency gyrotron with a pulse magnet has been successfully carried out in a frequency range including 1 THz. In the experiments, the timing of an electron beam pulse injection is adjusted at the top of the magnetic field pulse, where the variation of field intensity is negligible. The operation cavity modes seem to be TE1, 12 and TE4,12 at the second harmonics. The corresponding frequencies are 903 GHz and 1,013 GHz, respectively. Additionally several features of radiation measurement results of the gyrotron are described and brief considerations are presented. 相似文献