Reliability of the doping concentration in an ultra-thin body and buried oxide silicon on insulator (SOI) and comparison with a partially depleted SOI

This study compares the reliability of nMOSFETs with low- and high-doped ultra-thin body and buried oxide (UTBB) with fully depleted (FD) and partially depleted (PD) silicon on insulator (SOI). The high-doped devices display lower off-current leakage performance but more degradation in both hot-carrier stress (HCS) and positive bias temperature instability (PBTI) test at both room temperature and elevated temperature compared with the low-doped devices. The PBTI test indicates that the high-doped devices induce high tunneling leakage and that the degradation is highly associated with temperature. The degradation stabilizes with an increase in stress time. The thinner PD-SOI demonstrates low variation at the threshold voltage and low drive current under HCS. The FD-SOI has better drain leakage control than the PD-SOI.     

基于数字信息技术的智能环卫系统开发

随着生活水平提高,环境卫生已是被广泛关注的问题,由于目前环卫监管技术手段的不完善,违规倾倒、倒买倒卖现象时有发生,对周边居民生活、环境带来了极大损害。文章提出了一种RFID(无线射频动态存取技术)、GPS(全球定位技术)、GPRS(移动通讯技术)、GIS(地理信息技术)等多项数字信息技术于一体,对环卫车辆统一管理的信息化系统平台。从功能上,设计了在途车载终端和车辆监控平台两个子系统。其中,在途车载终端完成车载货物重量信息、定位信息、电子标签信息的数据采集,通过GPRS无线上传至服务器平台。监控平台可实时观测车辆的作业位置、行驶路线、有无违章行为,并进行量化统计,生成收集垃圾的数据报表,作为分析和考评的依据。该系统平台经实际使用,能达到预期效果,车载系统符合国家安全管理规定,在环卫行业监管工作中,具有很高实用价值和推广意义。     

A 1-V 86-mW-RX 53-mW-TX Single-Chip CMOS Transceiver for WLAN IEEE 802.11a

A 1-V WLAN IEEE 802.11a CMOS transceiver integrates all building blocks on a single chip including a transformer-feedback VCO and a stacked divider for the frequency synthesizer and 8-bit IQ ADCs and 8-bit IQ DACs. Fabricated in a 0.18-mum CMOS process and operated at a single 1-V supply, the receiver and the transmitter consume 85.7 mW and 53.2 mW, including the frequency synthesizer, respectively. The total chip area with pads is 12.5 mm².     

Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme

Echo canceller plays an important role in the full-duplex communication system. Conventional implementations of echo cancellers are often the adaptive transversal filter architectures due to the simplicity and robustness of stability and convergence. However, the conventional echo cancellers suffer from high cost problem especially when the response time of the echo is long. In this paper, a new cost-efficient architecture of echo cancellers, targeting on 10GBase-T Ethernet System, is presented. The proposed scheme inherits the concept of channel shortening which is widely employed in DSL systems. A shortened impulse response filter is implemented at the receiver to shorten the impulse response of the echo signal. Hence, the overall cost of echo cancellers can be reduced. We generalize the channel shortening architecture to a joint multi-channel shortening scheme. The joint multi-channel shortening architecture can be applied to multiple-input multiple-output wireline communication systems to further reduce both the cost of echo and near-end crosstalk (NEXT) cancellers. We apply the proposed scheme to 10GBase-T Ethernet system. The simulation results show that the proposed echo and NEXT cancellers can save up to 35% hardware cost compared to the conventional transversal implementations.

Transient analysis of the impact stage of wirebonding on Cu/low-K wafers

In this paper, transient mechanical responses of the Cu/low-K structure during the impact stage of the wirebonding process were investigated. Parametric studies were carried out to examine the effect of elastic moduli of different constituent materials on the potential of structural defect on the copper via and the pad. The analysis applied the explicit time integration scheme, which is feasible in dealing with the nonlinear transient structural behavior.     

Novel design for small-size coplanar waveguide frequency tripler

This letter presents a novel design for a small-size coplanar waveguide frequency tripler. In this study, a new BPF has been replaced the conventional stub lines in the output termination of the multiplier. Not only enhance the performance of the tripler, but also reduce the whole circuit size. to 2.125/spl times/2.275 cm/sup 2/ in the frequency 0.8/2.4 GHz, The spurious suppressions are 37.48, 33.38, and 32.08 dBc for the 1st, 2nd, and 4th harmonics, respectively. It reveals the best output power of -1.92 dBm for a 0 dBm input signal and maximum conversion gain of -1.92 dB. It is very useful for applications in the wireless communication and radar systems.     

Algorithms of halftoning color images with edge enhancement

Printers usually generate a limited number of colors and lack the ability of producing continuous-tone color images. Traditional error-diffusion algorithms are used to solve this problem. Compared with other approaches, the approaches of using error-diffusion in general can generate halftoned images of better quality. However, smeared edges and textures may occur in these halftoned images. To produce halftoned images of higher quality, these artifacts due to unstable images, dot-overlap, and error-diffusion must be eliminated or reduced. In this paper, we show that unstable images can be eliminated or reduced through using a proper color difference formula to select the reproduction colors even vector error-diffusion is performed in the RGB domain. We also present a method of using different filters to halftone different components of a color. This approach may have clearer and sharper edges for halftoned color images. Unexpected colors may be generated due to dot-overlap in the printing process. We have presented a method to eliminate this color distortion in the process of error-diffusion. Halftoning a color image by our proposed error-diffusion algorithm with edge enhancement has the following characteristics: the unstable images do not exist; the color-error caused by dot-overlap is corrected; and the smeared edges are sharpened.     

Current Phase Lead Compensation in Single-Phase PFC Boost Converters With a Reduced Switching Frequency to Line Frequency Ratio

Traditional design of the current loop controller in a single-phase power factor correction boost converter is not suitable for applications with higher line frequencies (up to 800 Hz) because of the zero-crossing distortion and high harmonic content due to the current phase lead effect. Increasing the control bandwidth and switching frequency in order to avoid this effect would reduce converter efficiency and is objectionable. The paper presents the leading-phase admittance cancellation (LPAC) technique, which improves the current-shaping control structure and eliminates the current phase lead without increasing the bandwidth requirement. The LPAC method extends the allowable line frequency range from 1/150 to 1/5 of the current loop bandwidth. The LPAC method is load-invariant and superior to other previously proposed methods. The LPAC network can be added to existing designs, which would require only two passive components in the simplest case     

Growth of CdS Nanoneedles by Pulsed Laser Deposition

CdS nanoneedles have been grown on Ni-coated Si (100) substrates by pulsed laser deposition. Substrate temperature and Ni-catalyst layer thickness were found to have great effects on the density and morphology of the as-grown CdS nanoneedles. Crystalline CdS nanoneedles with middle diameter and length of about 40?nm to 100?nm and 400?nm to 1000?nm, respectively, could be obtained at 350°C to 450°C on Ni-coated silicon (100) substrates, and nanoneedles with good shapes were obtained at 400°C substrate temperature. From the cross-section morphologies, it was found that the CdS nanoneedles grew out of the base CdS crystallite layer with thickness of about 500?nm. Based on the experimental results, vapor?Csolid and vapor?Cliquid?Csolid growth modes describe the CdS nanoneedle growth.     

Characteristic of copper wire and transient analysis on wirebonding process

In the present paper, two major analyses are achieved. In the first, experimental procedures were accomplished to measure tensile mechanical properties of copper (Cu) wire (? = 1 mil) before/after electric flame-off (EFO). Characteristics of free air ball (FAB), heat affected zone (HAZ) and thermal stable zone (TSZ) in as-drawn wire have been carefully investigated by microhardness, self-design pull test fixture, nanoindentation and atomic force microscopy (AFM). A 2nd EFO real-time technique has been conducted to reduce the strength of Cu wire and increase the bonding region. Secondary, with the obtained experimental material data, a comprehensive finite element wirebonding model based on explicit time integration software ANSYS/LS-DYNA is developed to predict the overall strain/stress distributions on the aluminum (Al) bond pad. Finite element analysis (FEA) results demonstrate that plastic deformation on Al bond pad around smashed FAB can be reduced by increasing the surface roughness on FAB. A series of comprehensive parametric studies were conducted in this research.