Microscale Patterning of Mesoscopic PZN-PT Single Crystal Films by Crystal ion Slicing and Laser-Induced Etching

Advances in the fabrication of solid-solution single crystal relaxor ferroelectrics have made it possible to produce highly efficient piezoelectric crystals, and have attracted renewed interest in the use of these crystals for a new generation of piezoelectric transducers, actuators and sensors. Of particular interest is their incorporation into micro-electromechanical systems (MEMS). In this paper we report on the laser-induced wet chemical etching of lead zinc niobate-lead titanate (PZN-PT) in hydrochloric acid (HCl). Argon-ion laser radiation at power levels up to 4 W is focused to a spot diameter of about 15μm and results in the chemical etching of grooves at patterning speeds up to 5μm/sec. Crystal ion slicing, an ion-implant-based film separation technique, is used in combination with laser etching to form 5 to 10μm-thick patterned and freestanding films for incorporation into micro-electromechanical devices.     

Ethylene polymerization over MgO‐supported zirconocene catalysts

Supported zirconcene catalysts on a new support, MgO, were prepared and tested in ethylene polymerization. Three types of impregnation methods were employed to find an optimum supporting method for MgO. The direct impregnation of Cp₂ZrCl₂ on MgO showed low metal loading and polymerization activity, while the catalyst had a higher metal loading and polymerization activity when MgO was treated with methylaluminoxane (MAO) before supporting. Treatment of MgO with MAO during the supporting step invoked two types of catalytic sites, which was evidenced by the bimodal molecular weight distribution of the polymer products. MgO is considered to have potential as a support for metallocenes.     

An Analysis of Citation Counts of ETRI‐Invented US Patents

From its foundation until 2004, ETRI has registered over 1,000 US patents. This letter analyzes the characteristics of these patents and addresses the explanatory factors affecting their citation counts. For explanatory variables, research team related variables, invention specific variables, and geographical domain related variables are suggested. Zero‐altered count data models are used to test the impact of independent variables. A key finding is that technological cumulativeness, the scale of invention, outputs in the electronic field, and the degree of dependence on the US technology domain positively affect the citation counts of ETRI‐invented US patents. The magnitude of international presence appears to negatively affect the citation counts of ETRI‐invented US patents.     

多标准视频硬件解码器的存储器地址映射方法

提出了一种支持多标准视频的存储器地址映射方法,用一个简洁的公式把视频图像映射到DDR SDRAM的存储空间.该方法兼顾运动补偿模块、去块效应滤波模块(或重建模块)和显示模块的不同需求特点,通过充分减少DDR SDRAM非读写命令的额外延时,达到较高的存储器接口效率.     

TD-SCDMA系统终端中的GMM功能实体研究

移动性管理(MM,MobilityManagement)是层3的一个子层,它主要完成与用户的移动性相关的一些功能。根据业务的分域划分,MM子层被分为支持CS模式的MM实体和支持PS模式的GMM实体。本文通过对GMM一般过程和特殊过程的描述,介绍了TD-SCDMA系统终端GMM实体的功能及其实现过程。     

复合材料空心飞轮多环套装整体变形及应力简化精细分析

采用多环过盈装配是解决复合材料飞轮径向强度过低的有效途径之一。本文作者采用平面应力简化模型,提出了计及过盈配合后变形导致实际过盈量增大计算飞轮套装后的初终应力分布的方法;提出了基于叠加原理计算多环过盈装配旋转飞轮应力的方法;提出了保证飞轮旋转时配合界面不脱离的相关临界转速的概念和计算方法。算例分析表明:过盈配合后的变形对初终应力的影响不能忽略;过盈量和套装环数与飞轮的初终应力和相关临界转速有密切的关系。     

Synthesis of ZSM‐5 Films and Monoliths with Bimodal Micro/Mesoscopic Structures

A route to synthesize ZSM‐5 crystals with a bimodal micro/mesoscopic pore system has been developed in this study; the successful incorporation of the mesopores within the ZSM‐5 structure was performed using tetrapropylammonium hydroxide (TPAOH)‐impregnated mesoporous materials containing carbon nanotubes in the pores, which were encapsulated in the ZSM‐5 crystals during a solid rearrangement process within the framework. Such mesoporous ZSM‐5 zeolites can be readily obtained as powders, thin films, or monoliths.     

Passive alignment method of polymer PLC devices by using a hot embossing technique

A novel fabrication process using a hot embossing technique has been developed for micromechanical passive alignment of polymer planar lightwave circuit (PLC) devices. With only one step of embossing, single-mode waveguide straight channels and micropedestals for passive aligning are simultaneously defined on a polymer thin film with an accuracy of /spl plusmn/0.5 /spl mu/m. This process reduces the steps for fabricating alignment structures. A fabricated polymer PLC chip and fibers are combined on a v-grooved silicon optical bench (SiOB) in a flip-chip manner. The process provides a coupling loss as low as 0.67 dB per coupling face and a cost-effective packaging solution for various polymer PLC devices.     

Scaling planar silicon devices

The generation-over-generation scaling of critical CMOS technology parameters is ultimately bound by nonscalable limitations, such as the thermal voltage and the elementary electronic charge. Sustained improvement in performance and density has required the introduction of new device structures and materials. Partially depleted SOI, a most recent MOSFET innovation, has extended VLSI performance while introducing unique idiosyncrasies. Fully depleted SOI is one logical extension of this device design direction. Gate dielectric tunneling, device self-heating, and single-event upsets present developers of these next-generation devices with new challenges. Strained silicon and high-permittivity gate dielectric are examples of new materials that will enable CMOS developers to continue to deliver device performance enhancements in the sub-100 nm regime.     

Effects of SiN passivation and high-electric field on AlGaN-GaN HFET degradation

The authors report on the effects of silicon nitride (SiN) surface passivation and high-electric field stress (hot electron stress) on the degradation of undoped AlGaN-GaN power HFETs. Stressed devices demonstrated a decrease in the drain current and maximum transconductance and an increase in the parasitic drain series resistance, gate leakage, and subthreshold current. The unpassivated devices showed more significant degradation than SiN passivated devices. Gate lag phenomenon was observed from unpassivated devices and removed by SiN passivation. However, SiN passivated devices also showed gate lag phenomena after high-electric field stress, which suggests possible changes in surface trap profiles occurred during high-electric field stress test.