Detection and classification of defect patterns on semiconductor wafers

The detection of process problems and parameter drift at an early stage is crucial to successful semiconductor manufacture. The defect patterns on the wafer can act as an important source of information for quality engineers allowing them to isolate production problems. Traditionally, defect recognition is performed by quality engineers using a scanning electron microscope. This manual approach is not only expensive and time consuming but also it leads to high misidentification levels. In this paper, an automatic approach consisting of a spatial filter, a classification module and an estimation module is proposed to validate both real and simulated data. Experimental results show that three types of typical defect patterns: (i) a linear scratch; (ii) a circular ring; and (iii) an elliptical zone can be successfully extracted and classified. A Gaussian EM algorithm is used to estimate the elliptic and linear patterns, and a spherical-shell algorithm is used to estimate ring patterns. Furthermore, both convex and nonconvex defect patterns can be simultaneously recognized via a hybrid clustering method. The proposed method has the potential to be applied to other industries.     

Robust position control of DC servomechanism with output measurement noise

This note presents a systematic robust control method for DC servomechanism based on the sliding mode technique. The noise in the measured position is considered. The proposed approach guaranteed system robustness against parameter variations and external disturbances. The common requirement of an integral function in the formulation of sliding surface is eliminated. The position tracking error dynamics in the sliding mode is assigned. Several practical techniques for implementing the control scheme are provided as well.     

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).     

An automatic coefficient design methodology for high-order bandpass sigma-delta modulator with single-stage structure

An automatic coefficient design method for synthesis of bandpass sigma-delta modulators (BPSDMs) is presented in this brief. Single-stage BPSDM structures, cascade-of-resonator with distributed feedback, cascade-of-resonator with distributed feedforward, and a new structure with lower coefficient spread, are all used to fit the synthesized coefficients. The automatic coefficient design method is realized in an easy-to-use computer program. Even for inexperienced designers, reliable and high-tolerance BPSDM coefficients for various applications can be automatically and efficiently generated. The methodology covers many design concerns including BPSDM coefficient tolerance for circuit component mismatch, design tradeoffs among in-band noise suppression, oversampling ratio, modulator order and quantizer bit number. Finally, design examples with orders of 6 and 8, and quantizer bit number of 1-bit and 3-bit, respectively, are used for the verification of the proposed automatic coefficient design method.     

GaAsSb/InAlAs PA DHBTs Grown by Production MBE

The epi material growth of GaAsSb based DHBTs with InAlAs emitters are investigated using a 4 × 100mm multi-wafer production Riber 49 MBE reactor fully equipped with real-time in-situ sensors including an absorption band edge spectroscope and an optical-based flux monitor. The state-of-the-art hole mobilities are obtained from 100nm thick carbon-doped GaAsSb. A Sb composition variation of less than ± 0.1 atomic percent across a 4 × 100mm platen configuration has been achieved. The large area InAlAs/GaAsSb/InP DHBT device demonstrates excellent DC characteristics,such as BVCEO＞6V and a DC current gain of 45 at 1kA/cm2 for an emitter size of 50μm × 50μm. The devices have a 40nm thick GaAsSb base with p-doping of 4. 5 × 1019cm-3 . Devices with an emitter size of 4μm × 30μm have a current gain variation less than 2% across the fully processed 100mm wafer. ft and fmax are over 50GHz,with a power efficiency of 50% ,which are comparable to standard power GaAs HBT results. These results demonstrate the potential application of GaAsSb/InP DHBT for power amplifiers and the feasibility of multi-wafer MBE for mass production of GaAsSb-based HBTs.     

Triple-frequency planar monopole antenna for side-feed communication device on GSM/DCS/PCS operation

A novel side-feed planar monopole antenna capable of triple-frequency operation at about 900, 1800 and 1900 MHz is presented. The planar monopole antenna occupies a small area of 6/spl times/31 mm, and is easily made using thin copper. The planar monopole antenna can be side-fed and mounted perpendicularly to the main circuit board of a communication device so that it offers a novel design with a free degree of feed point so as to save device space, resulting in a low profile to the system ground plane. In addition, the obtained impedance bandwidths of the proposed antenna at about 900, 1800 and 1900 MHz can cover the GSM (890-960 MHz), DCS (1710-1880 MHz) and PCS (1850-1990 MHz) bands.     

电站锅炉燃烧稳定性诊断模型的研究

运用集总参数法建立炉膛的动态数学模型。应用前人提出的燃烧稳定性评价指数,该指数以燃烧过程能够克服的最大的燃料量的扰动来定量。通过仿真求出不同燃烧工况下对应的CSI值,以此作为评价燃烧稳定性的基准值,将实测的燃烧工况的CSI值与基准值相比较,据此对燃烧过程的稳定性做出评价。运行人员应以燃烧稳定性基准值为燃烧调整的目标,优化燃烧过程。     

Application of neural networks to prediction of phase transport characteristics in high-pressure two-phase turbulent bubbly flows

The phase transport phenomenon of the high-pressure two-phase turbulent bubbly flow involves complicated interfacial interactions of the mass, momentum, and energy transfer processes between phases, revealing that an enormous effort is required in characterizing the liquid–gas flow behavior. Nonetheless, the instantaneous information of bubbly flow properties is often desired for many industrial applications. This investigation aims to demonstrate the successful use of neural networks in the real-time determination of two-phase flow properties at elevated pressures. Three back-propagation neural networks, trained with the simulation results of a comprehensive theoretical model, are established to predict the transport characteristics (specifically the distributions of void-fraction and axial liquid–gas velocities) of upward turbulent bubbly pipe flows at pressures covering 3.5–7.0 MPa. Comparisons of the predictions with the test target vectors indicate that the averaged root-mean-squared (RMS) error for each one of three back-propagation neural networks is within 4.59%. In addition, this study appraises the effects of different network parameters, including the number of hidden nodes, the type of transfer function, the number of training pairs, the learning rate-increasing ratio, the learning rate-decreasing ratio, and the momentum value, on the training quality of neural networks.     

Analysis of flip-chip packaging challenges on copper/low-k interconnects

An interfacial-fracture-mechanics-based simulation methodology has been developed to study the flip-chip packaging effect on the copper/low-k structures. Multilevel submodeling techniques have been used to bridge the scale difference between the flip-chip packages and the metal/dielectric stacks. To achieve a smaller feature size and higher speed in future chips, SiO/sub 2/ can be replaced with low-k dielectric material in all via and trench layers or the number of metal layers can be increased. The effect of both packaging options has been evaluated. With either option, the future flip-chip copper/low-k packages are facing higher possibilities of adhesive or cohesive failure near the low-k interface. This paper provides a quantitative evaluation of the increased risk, thus providing guidelines to the next level of low-k flip-chip packages.