Novel single-stage second-order structure for low-pass wide-band low-power continuous-time filters

A novel single-stage second-order structure for Gm-C filters is presented. It allows ample reduction in hardware and thus power consumption. Moreover, due to exploiting otherwise parasitic poles, the structure allows much higher bandwidth than in conventional designs, be achieved. To verify effectiveness of new concept, and based on the new approach to implement second-order stages, a third-order and a fifth-order continuous-time low-pass filters were implemented. The filters fabricated in a CMOS process, achieved more than 430 MHz, bandwidth and less than THD for a 400 mV_p–p 100 MHz input signal. All these accomplished with a factor of about four reduction in hardware and power. The bandwidth, output voltage swing, and dynamic range are far larger than those of any other CMOS low-pass filters thus far reported, which have bandwidth higher than 100 MHz.     

A 125 GHz millimeter-wave phase lock loop with improved VCO and injection-locked frequency divider in 65 nm CMOS process

In this paper, a CMOS mm-wave phase locked loop (PLL) with improved voltage controlled oscillator (VCO) and injection-locked frequency divider (ILFD) at operational harmonic frequency 125 GHz is presented. The VCO structure uses the bulk effective and MOS varactor capacitor to adjust parasitic capacitor of the cross coupled pair. It obtains 2th harmonic frequency with 24% tuning range (110–140 GHz) by applying?±?1.2 V input voltage variation. The divide-by-4 ILFD circuit uses a cross coupled VCO with three injection transistors acting in linear and nonlinear regions. The frequency dividers such as divided-by-4 ILFD, subsequent current mode logic (CML) and true single phase clock (TSPC) as divider chain with ratio 1/256 are used to synthesize frequency 244 MHz which is compared to reference frequency, 244 MHz in the PLL. Simulation results of the proposed PLL circuit are obtained after extracting post layout (with total chip size of 0.29 mm²) in 65 nm CMOS standard technology and @ 1.2 V power supply voltage. The obtained results confirm theoretical relations and indicate that the proposed circuit has good figure of merit (FoM), and higher tuning range and lower die area than the recent designs.

     

Risk constrained self-scheduling of hydro/wind units for short term electricity markets considering intermittency and uncertainty

In view of the intermittency and uncertainty associated with both the electricity production sector of restructured power system and their competitive markets, it is necessary to develop an appropriate risk managing scheme. So that it is desirable to trade-off between optimum utilization of intermittent generation resources (i.e. renewable energy resources), uncertain market prices and related risks in order to maximize participants' benefits and minimize the corresponding risks in the multi-product market environment. The main goal of this paper is to investigate risk management by introducing a novel multi-risk index to quantify expected downside risk (EDR) which is caused by both the wind power and market price uncertainties. Value-at-Risk (VaR) method is used to assess the mentioned risk issue by the proposed weighted EDR, so that an optimal trade-off between the profit and risk is made for the system operations. Also, the roulette wheel mechanism is employed for random market price scenario generation wherein the stochastic procedure is converted into its respective deterministic equivalents. Moreover, the autoregressive integrated moving average (ARIMA) model is employed to characterize the stochastic wind farm (WF) generation by predetermined mean level and standard deviation of wind behavior as well as temporal correlation. The problem is formulated as a mixed-integer stochastic framework for a hydro-wind power system scheduling and tested on a generation company (GENCO).     

Semiconductor‐assisted self‐cleaning polymeric fibers based on zinc oxide nanoparticles

Self‐cleaning polymeric fibers have been successfully prepared by depositing ZnO nanoparticle onto wool and polyacrylonitrile (PAN) fibers with good compatibility and significant photocatalytic self‐cleaning activity using the sol‐gel process at ambient temperature. scanning electron microscopy, energy dispersive spectroscopy, transmission electron microscopy, diffuse reflectance spectroscopy, X‐ray diffraction, Brunauer‐Emmett‐Teller surface area analysis, and thermogravimetric analysis have been adopted as the characterization techniques. Transmission electron microscopy studies revealed presence of zinc oxide nanoparticles with 10–15 nm in size. Brunauer‐Emmett‐Teller measurement showed surface area of 48 m²/g for the ZnO nanoparticles. Photocatalytic activity of the self‐cleaning materials were tested by measuring the photo‐assisted degradation of methylene blue (MB) and eosin yellowish (EY) under ultraviolet‐visible illumination. The results indicate that both of the ZnO‐coated polyacrylonitrile and ZnO‐coated wool fibers acquire photocatalytic activity toward dyes degradation. The photocatalytic activity of the treated fibers is maintained upon several numbers of photodegradation cycles. This facile and cheap preparation technique can be also applied to new polymeric fabrics to produce self‐cleaning materials for industrial application. © 2011 Wiley Periodicals, Inc. J Appl Polym Sci, 2011     

Considering the business system’s complexity with a network approach

Business management involves collecting information, goods, and funds as they move from supplier to manufacturer to wholesaler to retailer to consumer. Such business comprises interconnected parts that can be fundamentally complex and dynamic. A disturbance in one subnet of the system may thus have an opposed impact on another subnets, thus disturbing the business. Disruptions can have expensive and extensive results. This research aims to improve an increased Bayesian network method to consider business disruptions. The goal is to develop strategies that can diminish the opposed impacts of the disruptions and improve overall system reliability. Two influence agents are specified: the Bayesian and junction lack influence agents. An industrial model is used to demonstrate the proposed application, making the business more reliable. Moreover, two network learning methodologies are reviewed to update the probabilities in a model. The neural network seems to be a more favorable updating tool.     

A new high-speed, high-resolution open-loop CMOS sample and hold

A new open loop, high resolution CMOS sample and hold (S/H) circuit is introduced in this article. This circuit is constructed based on a new method which leads to a great reduction in dependency of the storing charge of the holding capacitors to the charge injection of transistors. It is a combination of dummy switches and auxiliary capacitors in order to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it is reached to a great improvement in signal to noise and distortion ratio up to about 15 dB and it’s ENOB is equivalent with about 16 bits. Another advantages of our proposed design are it’s lower power dissipation and it’s high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the threshold voltage’s variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications.     

A Novel Method for Bandwidth and Phase Margin Enhancement of Folded-Cascode Amplifier

This article describes a method to enhance bandwidth and phase margin of conventional folded-cascode op amps. It achieves a larger bandwidth and/or phase margin in folded-cascode CMOS op amps than those of a conventional one in a given CMOS process. For the same bandwidth the new method allows a larger phase margin, and for a given phase margin a larger bandwidth can be obtained. Also, for equal bandwidth, power consumption of the new folded-cascode is lower than the traditional one with similar load.     

An ANFIS based fuzzy controller for corner compensation

As threshold voltage of CMOS transistors is the main parameter that takes effect from process variations, in this paper a novel method for corner detection is presented which senses the variations of fabrication process through threshold voltage of the devices. A new general purpose 2-input, 2-output, 25 rules, ANFIS based fuzzy controller is proposed to compensate the variations subsequently. In this controller novel structures are presented for each block including membership function generator, Min–Max selector and defuzzifier. As an application, bias points of comparators of a typical flash ADC are controlled through introduced system in order to compensate the process variation effects and minimizing total power consumption consequently. Due to differential structures used in the architecture of the blocks, major part of the power supply noise is rejected. The Hspice (level 49) simulation results are given using a generic 0.35 μm standard CMOS technology parameters and power supply of 3.3 V with total power consumption of 15.6 mW for 7.4 MFLIPS. Because of simple and symmetrical circuitry, layout of the proposed controller is very compact, about 410 μm × 210 μm.     

CMOS design of a four-quadrant multiplier based on a novel squarer circuit

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a ?3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz.