A universal ion implantation model for all species intosingle-crystal silicon

A physically based model for ion implantation of any species into single crystal silicon has been developed, tested and implemented in the ion implant simulator, UT-MARLOWE. In this model, an interpolation scheme, based on mathematical properties of ion-target interatomic potential, was employed and implemented to calculate the scattering process. Using this scheme, the resulting energy, direction and momentum of the ion and target can be derived from the existing scattering tables of UT-MARLOWE without calculating the entire scattering process. The method has advantages in terms of both accuracy and computational efficiency, as well as significantly reduced cost of code development. The impurity profiles and damage profiles predicted by the model simulations have been compared with secondary ion mass spectroscopy (SIMS) and Rutherford backscattering spectrometry (RBS), and excellent agreement with experimental data has been achieved     

Voltage- and temperature-dependent gate capacitance and current model: application to ZrO/sub 2/ n-channel MOS capacitor

Based on the energy-dispersion relation in each region of the gate-dielectric-silicon system, a tunneling model is developed to understand the gate current as a function of voltage and temperature. The gate capacitance is self-consistently calculated from Schrodinger and Poisson equations subject to the Fermi-Dirac statistics, using the same band structure in the silicon as used for tunneling injection. Franz two-band dispersion is assumed in the dielectric bandgap. Using a Wentzel-Kramer-Brillouin (WKB)-based approach, direct and Fowler-Nordheim (FN) tunneling and thermionic emission are considered simultaneously. The model is implemented for both the silicon conduction and valence bands and both gate- and substrate-injected currents. ZrO/sub 2/ NMOSFETs were studied through temperature-dependent C/sub g/-V/sub g/ and I/sub g/-V, simulations. The extracted band gaps and band offsets of the ZrO/sub 2/- and interfacial-Zr-silicate-layer are found to be comparable with the reported values. The gate currents in ZrO/sub 2/-NMOSCAPs are found to be primarily contributed from the silicon conduction band and tunneling appears to be the most probable primary mechanism through the dielectric. Oscillations of gate currents and kinks of gate capacitance were observed near the flat-band in the experiments. These phenomena might be caused by the interface states.     

Recent Developments in Semipolar InGaN Laser Diodes

Semiconductors - Group III-nitride semiconductors (GaN, AlN, and InN) are attractive materials for a wide range of electronic and photonic applications. The most widely employed growth plane for...     

Interconnect limits on gigascale integration (GSI) in the 21stcentury

Twenty-first century opportunities for GSI will be governed in part by a hierarchy of physical limits on interconnects whose levels are codified as fundamental, material, device, circuit, and system. Fundamental limits are derived from the basic axioms of electromagnetic, communication, and thermodynamic theories, which immutably restrict interconnect performance, energy dissipation, and noise reduction. At the material level, the conductor resistivity increases substantially in sub-50-nm technology due to scattering mechanisms that are controlled by quantum mechanical phenomena and structural/morphological effects. At the device and circuit level, interconnect scaling significantly increases interconnect crosstalk and latency. Reverse scaling of global interconnects causes inductance to influence on-chip interconnect transients such that even with ideal return paths, mutual inductance increases crosstalk by up to 60% over that predicted by conventional RC models. At the system level, the number of metal levels explodes for highly connected 2-D logic megacells that double in size every two years such that by 2014 the number is significantly larger than ITRS projections. This result emphasizes that changes in design, technology, and architecture are needed to cope with the onslaught of wiring demands. One potential solution is 3-D integration of transistors, which is expected to significantly improve interconnect performance. Increasing the number of active layers, including the use of separate layers for repeaters, and optimizing the wiring network, yields an improvement in interconnect performance of up to 145% at the 50-nm node     

An 8-bit low power DAC with re-used distributed binary cells architecture for reconfigurable transmitters

In this work an 8-bit DAC is presented which uses a new segmented architecture, where distributed binary cells are re-used in thermometric manner to realize the MSB unit cells. The DAC has been fabricated in 0.18 μm five-metal CMOS n-well process to be embedded in multi-standard reconfigurable wireless transmitters for low-speed applications. The proposed architecture has an inherent ability to reduce midcode glitch like the unary architecture, and the simulated midcode glitch is only 0.01 pV s. Simulation results show that the proposed DAC performs with an integral nonlinearity (INL) of 0.33 LSB and a differential nonlinearity (DNL) of 0.14 LSB. The DAC can achieve a maximum measured SFDR of 65.19 dB for 97.50 kHz signal at a sampling rate of 100 MSPS, without using any calibration or dynamic element matching (DEM) technique. For 1.07 MHz signal the measured SFDR is 56.84 dB at 100 MSPS sampling rate. At 50 MSPS sampling frequency and 146 kHz signal the SFDR of the DAC is 65.90 dB. The measured SFDR at 538 kHz signal is 63.62 dB for a sampling rate of 50 MSPS. Measured third order intermodulation distortion of the DAC is 58.55 dB, for a dual tone test with 1.03 MHz and 1.51 MHz signals at 50 MSPS sampling rate. Low power is also an important aspect in portable wireless devices. For 10.06 MHz signal and 100 MSPS sampling frequency, the power dissipation of the DAC is 20.74 mW with 1.8 V supply.     

Ultra-Thin Si<Subscript>1−<Emphasis Type="Italic">x</Emphasis></Subscript>Ge<Subscript><Emphasis Type="Italic">x</Emphasis></Subscript> Dislocation Blocking Layers for Ge/Strained Si CMOS Devices

We demonstrate ultra-thin (<150 nm) Si_1−x Ge _x dislocation blocking layers on Si substrates used for the fabrication of tensile-strained Si N channel metal oxide semiconductor (NMOS) and Ge P channel metal oxide semiconductor (PMOS) devices. These layers were grown using ultra high vacuum chemical vapor deposition (UHVCVD). The Ge mole fraction was varied in rapid, but distinct steps during the epitaxial layer growth. This results in several Si_1−x Ge _x interfaces in the epitaxially grown material with significant strain fields at these interfaces. The strain fields enable a dislocation blocking mechanism at the Si_1−x Ge _x interfaces on which we were able to deposit very smooth, atomically flat, tensile-strained Si and relaxed Ge layers for the fabrication of high mobility N and P channel metal oxide semiconductor (MOS) devices, respectively. Both N and P channel metal oxide semiconductor field effect transister (MOSFETs) were successfully fabricated using high-k dielectric and metal gates on these layers, demonstrating that this technique of using ultra-thin dislocation blocking layers might be ideal for incorporating high mobility channel materials in a conventional CMOS process.     

Effect of epitaxial realignment on the leakage behavior of arsenic-implanted,as-deposited polycrystalline Si-on-single crystal Si diodes

When dopants are indiffused from a heavily implanted polycrystalline silicon film deposited on a silicon substrate, high thermal budget annealing can cause the interfacial “native” oxide at the polycrystalline silicon-single crystal silicon interface to break up into oxide clusters, causing epitaxial realignment of the polycrystalline silicon layer with respect to the silicon substrate. Anomalous transient enhanced diffusion occurs during epitaxial realignment and this has adverse effects on the leakage characteristics of the shallow junctions formed in the silicon substrate using this technique. The degradation in the leakage current is mainly due to increased generation-recombination in the depletion region because of defect injection from the interface.     

Simulation of single phase non-Newtonian flow characteristics of heavy crude oil through horizontal pipelines

The effect of diameter, velocity, and temperature on flow properties of heavy crude oil in three horizontal pipelines using computational fluid dynamics (CFD) was studied. The flow characteristics were simulated by using CFD software, ANSYS Fluent 6.2. The mesh geometry of the pipelines having inner diameter of 1, 1.5, and 2 inch were created by using Gambit 2.4.6. From grid independent study, 221, 365 mesh sizes were selected for simulation. The CFD ANSYS Fluent 6.2 Solver predicted the flow phenomena, pressure, pressure drop, wall shear stress, shear strain rate, and friction factor. A good agreement between experimental and CFD simulated values was obtained.     

Multiple-band large-signal characterization of millimeter-wave double avalanche region transit time diode

A large-signal method based on non-sinusoidal voltage excitation model is used to study the DC and RF characteristics of Double Avalanche Region (DAR) Silicon Transit Time diode. A large-signal simulation program based on drift-diffusion model is developed for this study. The simulation results show the existence of several distinct negative conductance bands in the admittance characteristics separated by positive conductance. Thus the DAR device is capable of delivering RF power not only at the design frequency but also at several frequency bands higher than the design frequency band in the mm-wave regime. A comparative study with DDR Si device designed to deliver RF power at a particular mm-wave frequency band shows that DAR Si device is capable of delivering significantly higher RF power not only at the designed mm-wave frequency band, but also at higher frequency bands.     

Role of methods of blending on polymer–polymer compatibility

The role of methods of blend preparation on polymer-polymer compatibility was investigated. Three different types of methods of blending, such as solution-casting, melt-mixing, and coprecipitation, were applied for three types of blend systems, viz., poly(vinyl chloride-co-vinyl acetate) (VYHH)/polystyrene (PS), VYHH/poly(styrene-co-acrylonitrile) (SAN), and VYHH/poly(methyl methacrylate) (PMMA) by measuring their glass transition temperatures (T_g) by a differential scanning calorimeter (DSC). It has been found that compatibility of the polymers depends on the method of blending and compatibility also varies from one blend system to another. Among the various types of blending methods, the coprecipitation method of blending gives the best compatibility result. © 1996 John Wiley & Sons, Inc.