高速12位D/A转换器

介绍了高速12位D/A转换器的电路设计,采用2μm等平面高速双极工艺,研制出数据更新率≥80MHz,线性误差≤3LSB,微分非线性≤3LSB的12位D/A转换器电路.     

Design of Ultra-Wideband Monopulse Receiver

In this paper, we propose a novel amplitude-comparison monopulse receiver architecture for ultra-wideband radars. This monopulse receiver consists of four ridged-horn antennas placed in a square-feed configuration, a comparator circuit that generates the monopulse sum and difference signals, cross-correlation receivers that detect the monopulse signals, and an amplitude-comparison monopulse processor that determines the target's angular position. The derived monopulse sum and difference signals are verified through measurements. The derived sum and difference patterns are compared with measured patterns, and they show good agreements-measured 3-dB beamwidth=6.4deg(derived=6deg), measured unambiguous tracking range=plusmn5deg(derived=plusmn5deg), and measured sum pattern sidelobe level=-6 dB (derived=-8 dB)     

Exposed Die-Top Encapsulation Molding for an Improved High- Performance Flip Chip BGA Package

The recent advancement in high- performance semiconductor packages has been driven by the need for higher pin count and superior heat dissipation. A one-piece cavity lid flip chip ball grid array (BGA) package with high pin count and targeted reliability has emerged as a popular choice. The flip chip technology can accommodate an I/O count of more than five hundreds500, and the die junction temperature can be reduced to a minimum level by a metal heat spreader attachment. None the less, greater expectations on these high-performance packages arose such as better substrate real estate utilization for multiple chips, ease in handling for thinner core substrates, and improved board- level solder joint reliability. A new design of the flip chip BGA package has been looked into for meeting such requirements. By encapsulating the flip chip with molding compound leaving the die top exposed, a planar top surface can be formed. A, and a flat lid can then be mounted on the planar mold/die top surface. In this manner the direct interaction of the metal lid with the substrate can be removed. The new package is thus less rigid under thermal loading and solder joint reliability enhancement is expected. This paper discusses the process development of the new package and its advantages for improved solder joint fatigue life, and being a multichip package and thin core substrate options. Finite-element simulations have been employed for the study of its structural integrity, thermal, and electrical performances. Detailed package and board-level reliability test results will also be reported     

基于类渗流导电的超薄栅氧化层软击穿后的电流模拟

研究了超薄栅氧化层(≤3.0nm)软击穿(soft breakdown,SBD)后的栅电流和衬底电流特性.提出了一个基于类渗流导电的SBD后栅电流和衬底电流的解析公式--类渗流导电公式.该公式能够在较大的电压范围(-4～+3V)模拟氧化层SBD后的栅电流和衬底电流的电流-电压特性,为超薄栅氧化层可靠性的研究提供了一个较为简便的公式.     

一个适用于短沟HALO结构MOS器件的直接隧穿栅电流模型

对沟道长度从10μm到0.13μm,栅氧化层厚度为2.5nm的HALO结构nMOS器件的直接隧穿栅电流进行了研究,得到了一个适用于短沟道HALO结构MOS器件的直接隧穿栅电流模型.随着沟道尺寸的缩短,源/漏扩展区占据沟道的比例越来越大,源漏扩展区的影响不再可以忽略不计.文中考虑了源/漏扩展区对直接隧穿栅电流的影响,给出了适用于不同HALO掺杂剂量的超薄栅(2～4nm)短沟(0.13～0.25μm)nMOS器件的半经验直接隧穿栅电流模拟表达式.     

低阻p型衬底上高阻厚层n型外延

介绍了高阻厚层反型外延片的一种实用生产技术，即在PE-2061S外延设备上，采取特殊的工艺控制在电阻率小于0.02Ω·cm的p型低阻衬底上实现了高阻厚层n型外延生长，外延层电阻率大于40Ω·cm，厚度大于100μm. 研究表明：该外延材料完全可以满足IGBT器件制作的需要.     

基于BiCMOS技术的高速数字/模拟转换器

基于BiCMOS技术，进行了高速数字/模拟转换器研究. 以并行输入类型，电流工作模式的16位D/A转换器为载体，进行了电路设计、工艺制作和测试. 在±5.0V工作电压下，测试得到转换速率≥30MSPS，建立时间为50ns，增益误差为±8% FSR，积分非线性误差为1/2 LSB，功耗为500mW.     

一种用于超高频RFID阅读器的正交下变频混频器的分析与设计

分析了共用跨导级的正交下变频混频器的性能,包括电压转换增益、线性度、噪声系数和镜象抑制比,分析表明其在电流开关模式下比传统的Gilbert混频器对具有更好的性能.设计并优化了一个基于共用跨导级结构的用于超高频RFID阅读器的正交下变频混频器.在915MHz频段上,该混频器测得12.5dB的转换增益,10dBm的IIP3 ,58dBm的IIP2和17.6dB的SSB噪声系数.芯片采用0.18μm 1P6M RF CMOS工艺实现,在1.8V的电源电压下仅消耗3mA电流.     

本地WDM网络节点上波分复用设备的配置

本文对本地WDM网络节点上波分复用设备的配置进行了分析 ,认为在城域WDM网中一般只配前置放大器 ,而大本地网需在收端配前置放大器 ,发端配功率放大器 ,对于节点距离超过100km的情况下 ,需加线路放大器     

基于关键路径的三模冗余表决器插入算法

在FPGA的三模冗余设计中,寄存器的反馈环路会导致错误持续出现,严重影响三模冗余的容错性能,因此需要在寄存器的反馈环路上插入表决器。该文首次提出了一种针对映射后网表进行三模冗余设计的方法,同时提出了基于关键路径的表决器插入算法,该算法在表决器的插入时避开关键路径,缓解了三模冗余设计中插入表决器时增加延时的影响。与国外同类算法相比,该文算法在不降低电路可靠性的前提下,以不到1%的面积开销,使得关键路径延时减少3%~10%,同时算法运算速度平均提高35.4%。