A fully integrated switched-capacitor DC–DC converter with hybrid output regulation

In this paper, we propose a fully integrated switched-capacitor (SC) DC–DC converter with hybrid output regulation that allows a predictable switching noise spectrum. The proposed hybrid output regulation method is based on the digital capacitance modulation for fine regulation and the automatic frequency scaling for coarse regulation. The automatic frequency scaler and on-chip current sensor are implemented to adjust the switching frequency at one of the frequencies generated by a binary frequency divider with change in load current. Thus, the switching noise spectrum of the proposed SC DC–DC converter can be predicted over the entire load range. In addition, the bottom-plate losses due to the parasitic capacitances of the flying capacitors and the gate-drive losses due to the gate capacitances of switches are reduced at light load condition since the switching frequency is automatically adjusted. The proposed SC DC–DC converter was implemented in a 0.13 µm CMOS process with 1.5 V devices, and its measurement results show that the peak efficiency and the efficiency at light load condition are 69.2% and higher than 45%, respectively, while maintaining a predictable switching noise spectrum.     

A compact low-power algorithmic A/D converter implemented on a large scale FPAA chip

This paper presents an impact and low power algorithmic ADC which is implemented on a large scale field programmable analog array chip. The proposed circuit is merely composed of the elements within a single computational analog block (CAB) to minimize the area and parasitic effects. The feedback residue is amplified by a simple operational transconductance amplifier with a gain of \(-\,2\). Therefore, a new algorithm for the conversion process is proposed for this negative gain structure. Furthermore, owing to the floating-gate technique adopted in this work, the parameters and routes of the ADC achieve exceptional reconfigurability. The offset, reset, reference, threshold voltages, and gain all can be adjusted for optimizing the ADC performance. The measured results of the DNL is + 2/? 1 LSB and the INL is + 1.8/? 1.4 LSB, respectively. Under an 8-bit resolution and a 62.5 Hz sampling frequency condition, the measured effective number of bit is 7.6 bits. The total current consumption of the OTAs and FGOTAs is \(1.6\,\upmu\)A under a 2.5 V supply voltage. Each CAB which includes all components, switches, and routings occupies an area of \(400 \times 500\,{\mathrm{mm}}^2\).     

Nth order current mode universal filter using MOCCCIIs

This article presents a new current mode single-input-multiple-output nth order universal filter. The proposed circuit employs (n + 1) number multiple output second generation current conveyors and n number grounded capacitors only. Presented circuits can realize current mode low pass, high pass, band pass, notch and all pass responses simultaneously at different high output impedance terminals. The current mode filter circuit provides low input impedance by selecting the proper value of bias current and also has high output impedance, which is suitable for cascading. The circuit offers some important features such as resistor less realization, no passive component matching constraints, low sensitivity, electronic tunability and active-C realization. The functionality of the proposed filter circuit is tested with the PSPICE simulation, which is found to agree well with the proposed theory.     

A Cross-Layer Multi-Hop Simulator for IEEE 802.11e

In this work we simulate the ad hoc mode of IEEE 802.11e for routing optimisation. We simulate the behaviour of routing algorithms at the network layer by using a custom-made cross-layer network simulator developed by our team, which simultaneously considers the physical and Medium Access Control (MAC) layers. Although the simulator also supports the infrastructure mode, in this paper we focus on the ad hoc feature which was introduced by the authors. We opted for the simulator approach over the theoretical analysis, but we also present a mathematical model for IEEE 802.11 ad hoc networks. Some initial tests were performed by using a simple routing algorithm (to evaluate the behaviour of the system in terms of selection of the path between a source and a destination, and the correctness of the calculated metrics, which include end-to-end delay, packets lost, packets delivered), but more advanced cross-layer design solutions were also tested. When information from the physical and MAC layers is used as an input to the routing algorithm, improvements are achieved in the performance of the network. Several functions were compared and the algorithm that privileges shorter links accounting with the metric “collision rate” achieves the best results. When compared with a standard routing solution, this cross-layer approach allows to increase the number of packets delivered, while not significantly affecting the end-to-end delay of the packets.     

Mobility Enhancement Technology for Scaling of CMOS Devices: Overview and Status

The aggressive downscaling of complementary metal–oxide–semiconductor (CMOS) technology to the sub-21-nm technology node is facing great challenges. Innovative technologies such as metal gate/high-k dielectric integration, source/drain engineering, mobility enhancement technology, new device architectures, and enhanced quasiballistic transport channels serve as possible solutions for nanoscaled CMOS. Among them, mobility enhancement technology is one of the most promising solutions for improving device performance. Technologies such as global and process-induced strain technology, hybrid-orientation channels, and new high-mobility channels are thoroughly discussed from the perspective of technological innovation and achievement. Uniaxial strain is superior to biaxial strain in extending metal–oxide–semiconductor field-effect transistor (MOSFET) scaling for various reasons. Typical uniaxial technologies, such as embedded or raised SiGe or SiC source/drains, Ge pre-amorphization source/drain extension technology, the stress memorization technique (SMT), and tensile or comprehensive capping layers, stress liners, and contact etch-stop layers (CESLs) are discussed in detail. The initial integration of these technologies and the associated reliability issues are also addressed. The hybrid-orientation channel is challenging due to the complicated process flow and the generation of defects. Applying new high-mobility channels is an attractive method for increasing carrier mobility; however, it is also challenging due to the introduction of new material systems. New processes with new substrates either based on hybrid orientation or composed of group III–V semiconductors must be simplified, and costs should be reduced. Different mobility enhancement technologies will have to be combined to boost device performance, but they must be compatible with each other. The high mobility offered by mobility enhancement technologies makes these technologies promising and an active area of device research down to the 21-nm technology node and beyond.     

Use of flip ambiguity probabilities in robust sensor network localization

Collinear or near collinear placement of some sensors in a wireless sensor network causes the location estimates of nearby sensors to be sensitive to erroneous distance measurements which leads to large location estimation errors. These errors and the possible propagation of these errors to the entire network or a large portion of it, thereby causing larger estimation errors for some sensors’ locations, is a major problem in localization. This phenomenon is well described in rigid graph theory, using the notion of “flip ambiguity”. This paper considers arbitrary sensor neighborhoods of two dimensional sensor networks and formulates an analytical expression for the probability of occurrence of the flip ambiguity. Based on the derived probability expression, a methodology is proposed to make the localization algorithms robust by calculating such flip ambiguity probabilities and eliminating potentially poor location estimates as well as assigning confidence factors to the estimated locations to prevent them from ruining the subsequent localization steps. The efficiency of the proposed methodology is demonstrated via a set of simulations.     

RFID Transponder Collision Control Algorithm

Transponder collision problem can be significant when a large number of RFID (radio frequency identification) transponders exist in field. Most existing anti-collision algorithms can solve this problem. However, problem arises when all or part of these transponders are having identical UID (unique identification). This paper proposes a new transponder collision control algorithm to overcome overlapping that occurs among transponders with identical UID in RFID large scale deployment (e.g., in a large warehouse), so that the RFID reader can successfully identify the quantity of transponders for each particular UID with high identification accuracy. The proposed anti-collision algorithm adopts a modified version of frequency domain method by adding stochastic delays in time domain. The obtained results show that the proposed method can achieve optimum frequency bandwidth utilization and at the same time poses high identification accuracy (almost 100%) with low identification delay.     

Design Methodology for Offloading Software Executions to FPGA

Field programmable gate array (FPGA) is a flexible solution for offloading part of the computations from a processor. In particular, it can be used to accelerate an execution of a computationally heavy part of the software application, e.g., in DSP, where small kernels are repeated often. Since an application code for a processor is a software, a design methodology is needed to convert the code into a hardware implementation, applicable to the FPGA. In this paper, we propose a design method, which uses the Transport Triggered Architecture (TTA) processor template and the TTA-based Co-design Environment toolset to automate the design process. With software as a starting point, we generate a RTL implementation of an application-specific TTA processor together with the hardware/software interfaces required to offload computations from the system main processor. To exemplify how the integration of the customized TTA with a new platform could look like, we describe a process of developing required interfaces from a scratch. Finally, we present how to take advantage of the scalability of the TTA processor to target platform and application-specific requirements.     

Adaptive Modeling of Analog/RF Circuits for Efficient Fault Response Evaluation

In this paper, we propose a methodology for adaptive modeling of analog/RF circuits. This modeling technique is specifically geared towards evaluating the response of a faulty circuit in terms of its specifications and/or measurements. The goal of this modeling approach is to compute important test metrics, such as fail probability, fault coverage, and/or yield coverage of a given measurement under process variations. Once the models for the faulty and fault-free circuit are generated, we can simply use Monte-Carlo sampling (as opposed to Monte-Carlo simulations) to compute these statistical parameters with high accuracy. We use the error budget that is defined in terms of computing the statistical metrics and the position of the threshold(s) to decide how precisely we need to extract the necessary models. Experiments on LNA and Mixer confirm that the proposed techniques can reduce the number of necessary simulations by factor of 7 respectively, in the computation of the fail probability.     

Photoluminescence and Raman Spectroscopy of Polycrystalline ZnO Nanofibers Deposited by Electrospinning

The technique of electrospinning offers the advantage of growing nanowires in bulk quantities in comparison with traditional methods. We report optical studies of polycrystalline zinc oxide (ZnO) nanofibers (∼100 nm thick and 5 μm long) deposited by electrospinning. Photoluminescence from the nanofibers shows a near-ultraviolet (near-UV) peak corresponding to near-band-edge emission and a strong broad peak in the visible region from oxygen antisite and interstitial defects. Temperature-dependent photoluminescence spectroscopy reveals that different carrier recombination mechanisms are dominant at low temperature. Our Raman spectroscopy results demonstrate that characterization of the quasimodes of longitudinal optical (LO) and transverse optical (TO) phonons present in an ensemble of polycrystalline nanofibers tilted at various angles in addition to the dominant E ₂(high) mode provides a promising technique for assessing the quality of such randomly oriented nanowires.