Evanescently coupled photodiodes integrating a double-stage taper for 40-Gb/s applications-compared performance with side-illuminated photodiodes

The design, fabrication, and performance of double-stage taper photodiodes (DSTPs) are reported. The objective of this work is to develop devices compatible with 40-Gb/s applications. Such devices require high efficiency, ultrawide band, high optical power handling capability, and compatibility with low-cost module fabrication. The integration of mode size converters improves both the coupling efficiency and the responsivity with a large fiber mode diameter. Responsivity of 0.6 A/W and 0.45 A/W are achieved with a 6-/spl mu/m fiber mode diameter and cleaved fiber, respectively, providing relaxed alignment tolerances (/spl plusmn/1.6 /spl mu/m and /spl plusmn/2 /spl mu/m, respectively), compatible with cost-effective packaging techniques. DSTPs also offer a wide bandwidth greater than 40 GHz and transverse-electric/transverse-magnetic polarization dependence lower than 0.2 dB. Furthermore, a DSTP saturation current as high as 11 mA results in optical power handling greater than +10 dBm and a high output voltage of 0.8 V. These capabilities allow the photodiode to drive the decision circuit without the need of a broad-band electrical amplifier. The DSTP devices presented here demonstrate higher responsivities with large fiber mode diameter and better optical power handling capabilities and are compared with classical side-illuminated photodiodes.     

Effects of error variation in means of measurement on reliability parameters in engineering-system monitoring

A method is given for calculating the monitoring reliability parameters (MRP) for an engineering system with allowance for the drift in the measurement error of the means of measurement (MM). The approach is based on introducing a biased MM error distribution into the traditional formulas for the conditional probabilities of spurious and unobserved failure. The bias at the center of the distribution is determined by the systematic error at the given instant. An example is given to illustrate the performance in MRP calculation.Translated from Izmeritel'naya Tekhnika, No. 1, pp. 12–13, January, 1994.     

Transjugular intrahepatic portosystemic shunts (TIPS) in children

The transjugular intrahepatic portosystemic shunt procedure is an accepted treatment for adults with complications of portal hypertension. We performed a retrospective review of all pediatric TIPS placements performed at the University of California, San Francisco between 1990 and 1996. Twelve procedures were attempted in nine children, with a mean age (+/- SD) of 9.4 +/- 3.9 years (range, 5 to 15 years) and a mean weight of 31 +/- 18 kg (range, 16 to 70 kg). The indications for TIPS placement were portal hypertension complicated by chronic variceal hemorrhage not controlled with sclerotherapy (n = 7) and hypersplenism with thrombocytopenia (n = 2). TIPS placement was successfully completed initially in seven of nine (78%) patients. Unfavorable vascular anatomy was the cause of failure in two cases. The seven patients who underwent successful TIPS placement were followed up for an average of 136 days (range, 1 to 800 days); two still have patent shunts, three underwent liver transplantation, one had a splenorenal shunt after stenosis, and one died of underlying liver disease. Variceal bleeding was controlled in four of five patients who successfully underwent TIPS placement. Shunt occlusion occurred in four patients; patency was restored by transjugular shunt revision in three, and a splenorenal shunt was performed in one.     

Hybrid ARQ scheme employing TCM and packet combining

A new hybrid automatic repeat request scheme employing packet combining based on the Viterbi decoder is presented. It is shown that the proposed form of combining, together with a rearrangement of the signal constellation, can outperform similar forms of packet combining such as average diversity combining     

Novel level-identifying circuit for flash multilevel memories

This paper presents a high-speed, small-area circuit specifically designed to identify the levels in the read out operation of a flash multilevel memory. The circuit is based on the analog computation of the Euclidean distance between the current read out from a memory cell and the reference currents that represent the different logic levels. An experimental version of the circuit has been integrated in a standard double-metal 0.7-μm CMOS process with a die area of only 140×100 μm². Operating under a 5-V power supply, this circuit identifies the read-out current of a memory cell, and associates it with the appropriate logic level in 9 ns     

Voiced speech excitation synthesis using a sinusoidal model

A modification to the `shape-invariant' sinusoidal speech model is proposed, whereby the phases of the component sinewaves used for the excitation are made to add coherently at each glottal closure. Applied to pitch and time-scale modification, higher quality synthetic speech is produced when large changes are required     

Ideal amplifier spacing for reduction of Gordon-Haus jitter indispersion-managed soliton communications

Based on a variational analysis, the authors demonstrate that the noise-induced Gordon-Haus timing jitter in a dispersion-managed soliton transmission system can be substantially reduced by appropriate placement of the amplifiers