基于局部结构张量的红外图像背景抑制

文中将局部结构张量与双边滤波相结合,提出了一种基于局部结构张量的红外图像结构化背景抑制算法。该算法采用局部结构张量的标准差作为双边滤波的执行判定,并利用双边滤波加权系数实现背景估计,从而实现结构化背景抑制和目标信息增强。实验结果显示,与二维最小均方滤波和偏微分方程算法相比,该算法对含有弱小目标的复杂背景具有良好抑制效果。     

超声后RADA16-I短肽纳米纤维支架重组装及成胶的研究

RADA16-I自组装短肽水溶液中形成纳米纤维并在盐离子作用下触发成水凝胶.RADA16-I纤维被大功率超声打断为小的原纤维片段.用AFM、CD和流变仪研究超声后纤维的重组装及其成胶性质.实验发现,超声未破坏纳米纤维二级结构,纤维仍保持β-sheet构型,超声4h后,小片段重组装为500nm的纤维,纤维虽未恢复到原长度,但仍未丧失其触发成胶的能力,只是在相同触发时间内达不到超声前的储能模量G′.还研究了超声对纳米纤维和成胶性能的影响,并提出相应的分子模型,这有助于短肽生物材料的应用,并对淀粉样蛋白病变的机理有一定的启示作用.     

联合转炉放散炉气预热废钢的可行性分析

研究了转炉放散炉气在竖炉中预热废钢的传热规律,建立了废钢多孔介质中的瞬态非热平衡流固耦合模型;通过FLUENT模拟得出废钢传热特性曲线和废钢料层内部的温度分布,分析了废钢预热中料层高度、转炉放散炉气温度和进气速度对废钢温度及预热效率的影响.研究结果表明:在1 200℃炉气中,废钢经30 min预热后温度达到570.3℃,预热效率为38.3%;随着废钢料层高度从2.5 m降低到0.7 m,废钢温度从570.3℃升高到695.7℃,预热效率下降为13.3%;随着转炉放散炉气温度从1 200℃升高到1 600℃,废钢温度从570.3℃升高到734.4℃,预热效率上升为44.2%;随着进气速度从2.375 m/s降低到1.125 m/s,废钢温度从570.3℃下降到356.1℃,预热效率上升为54.5%.     

主网与配电网协调规划的评价指标和规划方法

城市110 kV变电站作为连接主网与配电网的纽带,其选址和供电范围的划分是主网与配电网协调(以下简称主配网协调)规划的关键.文中提出协调因子及主配网协调规划评价模型,强调以提高总体运行均衡性为目标的电网规划思想.首先对变电站的基本属性进行分析,提出由运行率和关联度构成的负重系数的概念;然后利用约束圆环协调规划范围,将负重系数作为权值,利用改进后的加权Steiner最小树理论优化变电站选址;进而确定变电站的容量及供电范围.实际算例表明,从主配网协调程度考虑,所提出方法的规划结果优于传统选址规划结果.     

海量配电网调度监测信息的非主行键倒排索引查询技术

为解决配电网调度监控系统数据体量不断增大导致数据检索速度越来越慢的问题,结合数据同步技术与倒排索引机制,提出了一种二级索引架构。使用数据库的同步组件与索引器生成非主行键索引,在搜索时先获得数据主行键,再根据主行键检索到需要的数据,完成非主行键检索,再利用倒排索引技术改变数据的信息结构,缩短检索时间。以某铁路局10 kV供电调度监控信息为算例,进行非主行键检索测试。结果表明:完成非主行键检索所用时间为161 ms,满足在配电网调度监控系统中对数据进行快速检索的工程应用需求。     

动态流量平衡阀结构优化与验证

针对动态流量平衡阀流量控制精度较低问题,依据孔板流量和同心环状缝隙流方程,初步设计阀芯开孔型线,提出压差补偿系数因子修正法对现有的型线公式进行了优化修正,基于大涡模拟(LES)湍流模型,数值模拟研究了优化前后动态流量平衡阀的流量控制精度和流量精度误差,对比分析阀芯开孔型线对阀内压力脉动强度的影响规律,并搭建流量测试试验...     

Organic Ferroelectric‐Based 1T1T Random Access Memory Cell Employing a Common Dielectric Layer Overcoming the Half‐Selection Problem

Organic electronics based on poly(vinylidenefluoride/trifluoroethylene) (P(VDF‐TrFE)) dielectric is facing great challenges in flexible circuits. As one indispensable part of integrated circuits, there is an urgent demand for low‐cost and easy‐fabrication nonvolatile memory devices. A breakthrough is made on a novel ferroelectric random access memory cell (1T1T FeRAM cell) consisting of one selection transistor and one ferroelectric memory transistor in order to overcome the half‐selection problem. Unlike complicated manufacturing using multiple dielectrics, this system simplifies 1T1T FeRAM cell fabrication using one common dielectric. To achieve this goal, a strategy for semiconductor/insulator (S/I) interface modulation is put forward and applied to nonhysteretic selection transistors with high performances for driving or addressing purposes. As a result, high hole mobility of 3.81 cm² V^?1 s^?1 (average) for 2,6‐diphenylanthracene (DPA) and electron mobility of 0.124 cm² V^?1 s^?1 (average) for N ,N ′‐1H,1H‐perfluorobutyl dicyanoperylenecarboxydiimide (PDI‐FCN₂) are obtained in selection transistors. In this work, we demonstrate this technology's potential for organic ferroelectric‐based pixelated memory module fabrication.     

Design of Readout Electronics System for Prototype LAr-based Direct Dark Matter Detector

The prototype readout electronics system of direct dark matter detection experiments, which is mainly based on high speed and high precision waveform sampling and high speed data transfer techniques, consists of multiple waveform digitization modules (WDMs) and one global trigger module (GTM). The WDM exploits high speed analog-to-digital converter to acquire signals from the photomultiplier tubes (PMTs). The GTM collects hit information from WDMs, generates system trigger signal and fans out synchronous clock to all WDMs via backplane buses. Based on offline pulse shape discrimination method, the nuclear recoil events from a PuC neutron source can be clearly distinguished from gamma events within the energy range of 80 pe (photoelectron) to 240 pe for gamma rays, which indicates the capability of fulfilling the requirements of LAr-based direct dark matter detection experiments in future.     

2×4 MIMO-OFDM系统中K-Best检测器的设计与实现

基于贝尔实验室V-BLAST结构构建了2×4 MIMO-OFDM系统模型,并确定了该模型下K-Best算法的K值。之后对K-Best检测器进行了硬件架构设计,采用Xilinx Virtex-5芯片对所设计检测器加以实现,并给出检测器资源消耗和时钟频率等性能指标,最后通过仿真验证检测器正确性。