Wide‐Band Fine‐Resolution DCO with an Active Inductor and Three‐Step Coarse Tuning Loop

This paper presents a wide‐band fine‐resolution digitally controlled oscillator (DCO) with an active inductor using an automatic three‐step coarse and gain tuning loop. To control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. To cover the wide tuning range, a three‐step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO tuning range is 58% at 2.4 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The phase noise of the DCO output at 2.4 GHz is –120.67 dBc/Hz at 1 MHz offset.     

基于FPGA 的SRIO 端点设计与实现

为提高芯片间及板间互连的带宽、灵活性和可靠性,提出一种基于FPGA(field programmable gate array)的SRIO(serial rapid IO)端点的设计方法.介绍RapidIO的应用,对SRIO IP核及其参数设置进行分析,结合Xilinx提供的官方例程,编写用户逻辑,完成FPGA与DSP的高速通信,测试结果表明:该设计具有较高的带宽,有一定的参考价值.     

Highly stable tunable dual-wavelength Q-switched fiber laser for DIAL applications

We demonstrate a stable dual-wavelength Q-switched fiber laser for applications in differential absorption Lidar with tunability in absolute wavelength over several nanometers and discrete tuning in wavelength spacing from 1.1 to 3.3 nm. Single longitudinal-mode operation is also achieved by employing Sagnac loop saturable absorber filter. The delayed self homodyne linewidth measurement of the dual-wavelength continuous-wave laser shows a very narrow spectral linewidth and frequency jitter (<40 kHz). The advantages of tunable wavelengths, narrow linewidth, temperature insensitivity, and high stability in an efficient, cost effective, rugged, compact and light system make it a promising technology for airborne Lidar systems.     

A 15 nm Ultra‐thin Body SOI CMOS Device' with Double Raised Source/Drain for 90 nm Analog Applications

Fully‐depleted silicon‐on‐insulator (FD‐SOI) devices with a 15 nm SOI layer thickness and 60 nm gate lengths for analog applications have been investigated. The Si selective epitaxial growth (SEG) process was well optimized. Both the singleraised (SR) and double‐raised (DR) source/drain (S/D) processes have been studied to reduce parasitic series resistance and improve device performance. For the DR S/D process, the saturation currents of both NMOS and PMOS are improved by 8 and 18%, respectively, compared with the SR S/D process. The self‐heating effect is evaluated for both body contact and body floating SOI devices. The body contact transistor shows a reduced self‐heating ratio, compared with the body floating transistor. The static noise margin of an SOI device with a 1.1 µm² 6T‐SRAM cell is 190 mV, and the ring oscillator speed is improved by 25 % compared with bulk devices. The DR S/D process shows a higher open loop voltage gain than the SR S/D process. A 15 nm ultra‐thin body (UTB) SOI device with a DR S/D process shows the same level of noise characteristics at both the body contact and body floating transistors. Also, we observed that noise characteristics of a 15 nm UTB SOI device are comparable to those of bulk Si devices.     

HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

Introduction High- k gate dielectrics have been extensivelystudied as alternates to conventional gate oxide( Si O2 ) due to the aggressive downscaling of Si O2thickness in CMOS devices,and hence the exces-sive gate leakage.Hf O2 has emerged as one...     

基于方向性小波子树分形图像编码的改进算法

本文在分析混合分形零树小波图像编码算法(FZW)优缺点的基础上，提出一种新的基于方向性小波子树的分形图像编码算法。该算法结合零树小波编码和分形编码，通过在匹配搜索过程中使用方向性range和domain子树，提高匹配精度，改善了传统分形小波图像压缩中的方块效应，更大限度的保留了图像的边缘信息。实验结果表明，该算法在提高压缩比和去除图像的方块效应方面，均取得了良好的效果。     

Matrix unit cell scheduler (MUCS) for input-buffered ATM switches

This paper presents a novel matrix unit cell scheduler (MUCS) for input-buffered asynchronous transfer mode (ATM) switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-buffered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and verified using HSPICE. The circuit features a regular structure, minimal interconnects, and a low transistor count. HSPICE simulation indicates that using 2-μm CMOS technology, the MUCS circuit can operate at clock frequency of 100 MHz     

Statistical estimation of average power dissipation usingnonparametric techniques

In this paper, we present a new statistical technique for estimation of average power dissipation in digital circuits. The present parametric statistical technique estimates the average power based on the assumption that the power distribution can be characterized by a preassumed function. Large error can incur when the assumption is not met. On the other hand, the existing nonparametric technique, although accurate, is too conservative and requires a large sample size in order to achieve convergence. For a good tradeoff between simulation accuracy and computational efficiency, we propose a new nonparametric technique using the properties of the order statistics. It is generally applicable to any type of circuit irrespective of its power distribution function. Compared to the existing nonparametric technique, it is much more computationally efficient since it requires a much smaller sample size to achieve the same accuracy specification. This new technique is implemented in the distribution-independent power estimation tool (DIPE). DIPE is empirically demonstrated to be more robust and accurate than the parametric technique     

Vertex-based inter-frame boundary encoding scheme

The boundary is approximated by a polygon which can be encoded with the smallest number of bits for maximum distortion. The temporal redundancy between two successive frames is efficiently removed with the proposed scheme, resulting in a lower bit rate than the conventional algorithms