Application of Support Vector Machines in Assessing Conceptual Cost Estimates

Total conceptual cost estimates and the assessment of the quality of these estimates are critical in the early stages of a building construction project. In this study, the support vector machine (SVM) model for assessing the quality of conceptual cost estimates is proposed, and the application of SVM in construction areas is investigated. The results show that the SVM model assessed the quality of conceptual cost estimates slightly more accurately than the discriminant analysis model. This shows that using the SVM has potential in construction areas. In addition, the SVM model can assist clients in their evaluation of the quality of the estimated cost and the probability of exceeding the target cost, and in their decision on whether or not it is necessary to seek a more accurate estimate in the early stages of a project.     

Fast DCT algorithm with fewer multiplication stages

A novel fast DCT scheme with reduced multiplication stages and fewer additions and multiplications is proposed. The proposed algorithm is structured so that most multiplications tend to be performed at the final stage, which reduces the propagation error that could occur in the fixed-point computation. Minimisation of the multiplication stages can further decrease the error     

A time-domain approach to transmission network equivalents viaProny analysis for electromagnetic transients analysis

This paper presents a method of obtaining transmission network equivalents from the network's response to a pulse excitation signal. The proposed method is based on modal decomposition representation for the large-scale interconnected system. In this framework we use Prony analysis to identify the network function of the system and to decompose the large system into a parallel combination of simple first-order systems. As a result the network function of the transmission network can be identified easily, and a Thevenin-type of discrete-time filter model can be generated. It can reproduce the driving-point impedance characteristic of the network. Furthermore, the proposed model can be implemented into the EMTP in a direct manner. The simulation results with the full system representation and the developed equivalent system showed a good agreement     

Effect of the pressure drop rate on cell nucleation in continuous processing of microcellular polymers

Microllular plastics are cellular polymers characterized by cell densities greater than 10⁹ cells/cm³ and cells smaller than 10 μm. One of the critical steps in the continuous production of microcellular plastics is the promotion of high cell nucleation rates in a flowing polymer matrix. These high nucleation rates can be achieved by first forming a polymer/gas solution followed by rapidly decreasing the solubility of gas in the polymer. Since, in the processing range of interest, the gas solubility in the polymer decreases as the pressure decreases, a rapid pressure drop element, consisting of a nozzle, has been employed as a continuous microcellular nucleation device. In this paper, the effects of the pressure drop rate on the nucleation of cells and the cell density are discussed. The experimental results indicate that both the magnitude and the cell density are discussed. The experimental results indicate that both the magnitude and the rate of pressure drop play a strong role in microcellular processing. The pressure phenomenon affects the thermodynamic instability induced in the polymer/gas solution and the competition between cell nucleation and growth.     

Self-aligned offset gated poly-Si TFTs with a floating sub-gate

We have fabricated a self-aligned offset-gated poly-Si thin film transistor (TFT) by employing a novel photoresist reflow process. The gate structure of the new device is consisted of two unique patterns: A main-gate and a sub-gate. The new fabrication method extends the gate-oxide over the offset region. With the assistance of the sub-gate and reflowed photoresist a self-aligned offset region is successfully obtained due to the offset oxide acting as an implantation mask. The poly-Si TFT with symmetrical offsets is easily fabricated and the new method does not require any additional offset mask step. Compared with the misaligned offset gated poly-Si TFTs, excellent symmetric electrical characteristics are obtained     

Modified atmosphere packaging of a mixed prepared vegetable salad dish

The aim of this study was to design a modified atmosphere package for a mixed vegetable salad consisting of 75 g of cut carrot, 55 g of cut cucumber, 20 g of sliced garlic and 50 g of whole green pepper. Respiration data of all the components were combined with film permeability data to predict package atmospheres and design optimal packages for experimental testing for improved shelf-life of the produce. The optimal package avoided minimum O₂ and maximum CO₂ tolerance limits, and chilling injury temperatures for any component. A pouch form package made of 27 mm low density polyethylene developed a modified atmosphere of 2.0–2.1% O₂ and 5.5–5.7% CO₂, which was beneficial for all components and provided better quality retention than other test packages.     

A neural network-based power system stabilizer using power flowcharacteristics

A neural network-based power system stabilizer (neuro-PSS) is designed for a generator connected to a multi-machine power system utilizing the nonlinear power flow dynamics. The use of power flow dynamics provides a PSS for a wide range of operation with reduced size neural networks. The neuro-PSS consists of two neural networks: neuro-identifier and neuro-controller. The low-frequency oscillation is modeled by the neuro-identifier using the power flow dynamics, then a generalized backpropagation-through-time (GBTT) algorithm is developed to train the neuro-controller. The simulation results show that the neuro-PSS designed in this paper performs well with good damping in a wide operation range compared with the conventional PSS     

A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor

A 4-MB L2 data cache was implemented for a 64-bit 1.6-GHz SPARC(r) RISC microprocessor. Static sense amplifiers were used in the SRAM arrays and for global data repeaters, resulting in robust and flexible timing operation. Elimination of the global clock grid over the SRAM array saves power, enabled by combining the clock information with array select signals. Redundancy was implemented flexibly, with shift circuits outside the main data array for area efficiency. The chip integrates 315 million transistors and uses an 8-metal-layer 90-nm CMOS process.