The effects of maturation on early and late phases of phrenic neurogram during eupnea

In this paper, we investigate the effects of maturation on the early and late phases of the phrenic neurogram. We have used the matching pursuit (MP) method to examine the effects of maturation on breathing patterns in both time and frequency domains. The MP was chosen since the wavelet transform method may not represent signals whose Fourier transforms have a narrow high-frequency support. The phrenic neurogram was recorded from 25 piglets (3-35 days) during eupnea (normal breathing) at three postnatal age groups: young (3-7 days (n = 9)), (middle) 10-21 days (n = 6), and old (29-35 days (n = 10)). The energy percentage of atoms representing the nonperiodic neural activities (NPNAs) significantly decreased from young age to middle age groups (p<0.01) and from young age to old age groups (p<0.01), and from middle age to old age groups (p<0.055) in the early phase (the first half) of the phrenic neurogram, but these changes were not statistically significant in the late phase (the second half) of the phrenic neurogram as maturation proceeded. However, the energy percentage of atoms representing the periodic neural activities (PNAs) decreased with maturation, but these changes were not statistically significant in the early phase of the phrenic neurogram. The energy percentage of (PNAs) increased in the late phase of the phrenic neurogram as maturation proceeded although these changes were only significant between young and old age groups (p<0.01). These results suggest that the significant decrease of the NPNAs in the early phase and the increase in the late phase of the phrenic neurogram could be a sign of maturation in piglets.     

Electrochemical protein chip with arrayed immunosensors with antibodies immobilized in a plasma-polymerized film

An electrochemical protein chip was microfabricated. A thin-film three-electrode system, including an array of 36 platinum working electrodes, a set of thin-film Ag/AgCl electrodes, and platinum auxiliary electrodes, was integrated on a glass substrate. Capture antibodies were immobilized in a 4.5-nm-thick double layer of a hexamethyldisiloxane plasma-polymerized film. Because of their highly cross-linked network structure, the capture antibodies could be firmly immobilized. No nonspecific adsorption was observed during a series of procedures to detect target proteins, and electrochemical cross talk between neighboring sites was negligible. The sandwich immunoassay was conducted on a single chip using model proteins, alpha-1-fetoprotein and beta2-microglobulin. A distinct current increase following the oxidation of hydrogen peroxide produced by the enzymatic reaction of glucose oxidase was observed, which indicates that the capture proteins could actually bind the target proteins. Two kinds of protein were detected independently on multiple sites with respective capture antibodies.     

Advanced CD Control Technology for 65-nm Node Dual Damascene Process

This paper describes an advanced critical dimension (CD) control technology for a 65-nm node dual damascene process and beyond. A newly developed deposition enhanced shrink etching (DESE) process was introduced into both via and trench etching. This technology realizes not only dynamic via shrink ranging 40 nm but also accurate trench CD control by feedforward technology. Etching performance was investigated by electrical results of 65-nm Cu/low-k interconnects using porous chemical-vapor deposition SiOC. The 100% yields of 60-M via chains verified the DESE process robustness.     

Microprocessors in electric power systems

The present status of microprocessor applications in various fields of electric power systems is summarized. Special attention is directed towards development trends in the protection field where microprocessor applications are expected to cope with the increasingly stringent requirements for electric power supply reliability. Also discussed are the history, roles, design philosophy and basic schemes of microprocessor-based protective relaying systems. Only recently has their application reached a practical stage after long-term study and repeated field tests.     

Adaptive Ray‐bundle Tracing with Memory Usage Prediction: Efficient Global Illumination in Large Scenes

This paper proposes an adaptive rendering technique for ray‐bundle tracing. Ray‐bundle tracing can be done by per‐pixel linked‐list construction on a GPU rasterization pipeline. This rasterization based approach offers significant benefits for the efficient generation of light maps (e.g., hardware acceleration, tessellation, and recycling of shaders used in real‐time graphics). However, it is inapplicable to large and complex scenes due to the limited capacity of the GPU memory because it requires a high‐resolution frame buffer and high‐capacity node buffer for the linked‐lists. In addition, memory overflow can potentially occur on the per‐pixel linked‐list since the memory usage of the lists is usually unknown before the rendering process. We introduce an adaptive tiling technique with memory usage prediction. Our method uses an appropriately tiled frame buffer, thus eliminating almost all of the overflow risks thanks to our adaptive tile subdivision scheme. Using this technique, we are able to render high‐quality light maps of large and complex scenes which cannot be computed using previous ray‐bundle based methods.     

Surface properties of carbon micro-coils oxidized by a low concentration of oxygen gas

Vapor-grown carbon micro-coils were oxidized under a low O₂ flow-rate for introducing oxygen-containing functional groups on the surface. The surface characteristics were then examined. The O1s/C1s intensity ratios of the XPS spectra measured on the surface increased on using the oxidation treatment. The maximum O1s/C1s ratio of 11.4 at.% was obtained under the following conditions: (a) the flow-rate of the mixed gas of O₂+Ar (O₂/Ar=1/10) was 82.5 sccm; (b) the oxidation temperature was 600°C; and (c) the treatment time was 30 min. The maximum O1s/C1s ratio is about 3.5 times that of the source carbon coils. The specific surface area significantly increased due to the oxidation treatment and attained a maximum value of 1050 m² g⁻¹, which is about 10 times that of the source carbon coils. As the specific surface area increased, the surface morphology of the carbon coils became more complicated on a nanometer scale.     

New monolithic AGC amplifier stabilising output DC level for 560 Mbit/s optical transmission

A new AGC amplifier stabilising the output DC level is proposed and monolithically integrated using 1 ?m Si-bipolar IC technology. First, it is proven that the proposed AGC amplifier is about ten times superior to the conventional one in regard of output DC level stability. Next, it is confirmed that the IC, which exhibits a 720 MHz bandwidth, 39 dB maximum gain and 60 dB gain dynamic range, is feasible for 560 Mbit/s optical transmission.     

A DC-coupled wide dynamic range AGC amplifier IC for 560-Mbit/s optical transmission

A wide-band high-gain AGC amplifier stabilizing the output dc level against a broad gain variation is proposed and monolithically integrated using high-speed 1-μm Si-bipolar IC technology. The fabricated IC exhibits a maximum gain of 39 dB, gain dynamic range of 44 dB, bandwidth of 800 MHz, and output dc-level fluctuation of 8 mV, and realizes wide dynamic range and direct dc-coupling of the multistage AGC amplifier. Also, in order to examine the feasibility of the fabricated IC, a 1.5-μm-wavelength optical transmission experiment was carried out using DFB-LD and InGaAs-APD. Measured minimum received optical power for an error rate of 10^-9is -40 dBm at 560 Mbit/s and -38 dBm at 1.12 Gbit/s. Optical dynamic range of 30 dB is also achieved by using the fabricated IC and APD.     

A 250-Mb/s/pin, 1-Gb double-data-rate SDRAM with a bidirectionaldelay and an interbank shared redundancy scheme

This paper describes three circuit technologies indispensable for high-bandwidth multibank DRAM's. (1) A clock generator based on a bidirectional delay (BDD) eliminates the output skew. The BDD measures the cycle time as the quantity charged or discharged of an analog quantity, and replicates it in the next cycle. This achieves a 0.18-mm ², two-cycle-lock clock generator operating from 25 to 167 MHz with a 30-ps resolution. (2) A quad-coupled receiver eliminates the internal skew caused by the difference between a rise input and a fall input by 40%. (3) An interbank shared redundancy scheme (ISR) with a variable unit redundancy (VUR) efficiently increases yield in multibank DRAM's. The ISR allows redundancy match circuits to be shared with two or more banks. The VUR allows the number of units replaced to be variable. These circuit technologies achieved a 250-Mb/s/pin, 8-bank, 1-Gb double-data-rate synchronous DRAM