Nanoimprinting using release-agent-coated resins

A fluorinated self-assembled monolayer (F-SAM) is mainly used as the antisticking layer. To prevent the F-SAM coated on the nanoimprint lithography (NIL) mold from deteriorating, we propose a new form of nanoimprinting using a release-agent-coated resin. The results from measuring the surface free energy and observations by scanning probe microscopy (SPM) confirmed that the surface free energy, frictional force, and adhesion force of the release-agent spray-coated polymethylmethacrylate (PMMA) were lower than those of PMMA. To prove the release-agent spray-coated PMMA had a releasing effect, we tried to undertake thermal nanoimprinting on it using a mold without F-SAM. The pattern was clearly imprinted on the resin without any signs of adhesion.     

A Class of Sequential Blind Source Separation Method in Order Using Swarm Optimization Algorithm

We consider the problem of sequential, blind source separation in some specific order from a mixture of sub- and sup-Gaussian sources. Three methods of separation are developed, specifically, kurtosis maximization using (a) particle swarm optimization, (b) differential evolution, and (c) artificial bee colony algorithm, all of which produce the separation in decreasing order of the absolute kurtosis based on the maximization of the kurtosis cost function. The validity of the methods was confirmed through simulation. Moreover, compared with other conventional methods, the proposed method separated the various sources with greater accuracy. Finally, we performed a real-world experiment to separate electroencephalogram (EEG) signals from a super-determined mixture with Gaussian noise. Whereas the conventional methods separate simultaneously EEG signals of interest along with noise, the result of this example shows the proposed methods recover from the outset solely those EEG signals of interest. This feature will be of benefit in many practical applications.     

CaPPS: cache partitioning with partial sharing for multi-core embedded systems

As the number of cores in chip multi-processor systems increases, the contention over shared last-level cache (LLC) resources increases, thus making LLC optimization critical, especially for embedded systems with strict area/energy/power constraints. We propose cache partitioning with partial sharing (CaPPS), which reduces LLC contention using cache partitioning and improves utilization with sharing configuration. Sharing configuration enables the partitions to be privately allocated to a single core, partially shared with a subset of cores, or fully shared with all cores based on the co-executing applications’ requirements. CaPPS imposes low hardware overhead and affords an extensive design space to increase optimization potential. To facilitate fast design space exploration, we develop an analytical model to quickly estimate the miss rates of all CaPPS configurations using the applications’ isolated LLC access traces to predict runtime LLC contention. Experimental results demonstrate that the analytical model estimates cache miss rates with an average error of only 0.73 % and with an average speedup of \(3505\times \) as compared to a cycle-accurate simulator. Due to CaPPS’s extensive design space, CaPPS can reduce the average LLC miss rate by as much as 25 % as compared to baseline configurations and as much as 14–17 % as compared to prior works.     

A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.     

A distributed range-free correction vector based localization refinement algorithm

Localization problem is an important and challenging topic in today’s wireless sensor networks. In this paper, a novel localization refinement algorithm for LAEP, which is a range-free localization algorithm by using expected hop progress, has been put forward. The proposed localization refinement algorithm, called as CVLR, is based on position correction vectors and can resolve the LAEP’s hop-distance ambiguity problem, which can lead to adjacent unknown nodes localized at the same or very close positions. CVLR can make full use of the relative position relationship of 1-hop neighboring nodes (called as CVLR1), or 1-hop and 2-hop neighboring nodes (called as CVLR2), to iteratively refine their localization positions. Furthermore, from localization accuracy and energy dissipation perspective, we optimize the communication process of CVLR2 and propose an energy-efficient improved CVLR. Simulation results show that the localization accuracy of CVLR1, CVLR2, and the improved CVLR are obviously higher than that of LAEP and DV-RND.     

High SNR sum capacity analysis of BD MIMO BC systems with imperfect CSI

We investigate the sum capacity of Block Diagonalization precoding Multiple Input Multiple Output Broadcast Channels (BD MIMO BC) with imperfect Channel State Information (CSI) at the base station. Since it is difficult to obtain the exact expression, a lower and an upper bounds of the sum capacity under Gaussian channel estimation errors are drived instead. Analyses show that the gap between two bounds is considerably tight at all Signal to Noise Ratio (SNR) region. From the lower bound of the sum capacity, we can see that the multiplexing gain tends to be zero at high SNR region, which indicates that the BD MIMO BC system with channel estimation errors is interference-limited at high SNR.     

Inverse QR iterative method for subspace tracking

The Bi-LS method based on QR decomposition provides a convenient framework for developing efficient subspace tracking algorithms. To overcome the shortcoming of the backsubstitution step and improve the parallel architecture of the Bi-LS algorithms, a Bi-LS subspace tracking algorithm based on Inverse QR (IQR) decomposition is developed. The proposed IQR iterative algorithm for subspace tracking is well suited for the parallel implementation in the systolic array. Simulation results are presented to illustrate the effectiveness of the proposed IQR subspace tracking algorithm.     

An adaptive digital image watermark algorithm based on gray-scale morphology

An adaptive digital image watermark algorithm with strong robustness based on gray-scale morphology is proposed in this paper. The embedded strategies include: The algorithm seeks and ex-tracts adaptively the image strong texture regions. The algorithm maps the image strong texture region to the wavelet tree structures, and embeds adaptively watermark into the wavelet coefficients corre-sponding to the image’s strong texture regions. According to the visual masking features, the algorithm adjusts adaptively the watermark-embedding intensity. Experimental results show the algorithm is robust to compression, filtering, noise as well as strong shear attacks. The algorithm is blind watermark scheme. The image strong texture region extraction method based on morphology in this algorithm is simple and effective and adaptive to various images.     

Solution-Processed High-<Emphasis Type="Italic">k</Emphasis> Dielectric,ZrO<Subscript>2</Subscript>, and Integration in Thin-Film Transistors

We report a sol–gel method to deposit a high-k dielectric, zirconium oxide (ZrO₂). This solution-based approach has advantages of easy processing and low fabrication cost. Effects of annealing temperatures on dielectric properties, such as tunneling current density and capacitance density, are reported. Morphological and chemical characterizations suggest that the process temperature can be kept at or below 300°C. We have employed the solution-processed ZrO₂ dielectric in a zinc tin oxide thin-film transistor. Saturation mobility of 4.0 cm²/V s at operating voltage of 2 V has been observed. The measured subthreshold swing is 74 mV/decade, which is the result of the combination of an electronically clean dielectric/semiconductor interface and high insulator capacitance.