Photodetectors monolithically integrated on SOI substrate foroptical pickup using blue or near-infrared semiconductor laser

We made photodetectors on a silicon-on-insulator (SOI) substrate by a 0.35-μm BiCMOS fabrication process to detect the signal light used in an optical disk system. Investigating their characteristics at two wavelengths, 410 and 780 nm, for different structures, we found that the thickness of the silicon crystalline layer on the insulator strongly affected the frequency response at the longer wavelength, while the cutoff frequency was over 500 MHz for the shorter wavelength. We also simulated the frequency response     

Compaction of IDDQ Test Sequence Using Reassignment Method

IDDQ testing is an effective method for detecting short faults of CMOS circuits. Since IDDQ testing requires the measurement of current, the testing time of IDDQ testing is longer than that of logical testing. In this paper, we proposed an IDDQ test compaction method for internal short faults of gates in sequential circuits by using the reassignment method of signal values. Experimental results show that test sequences generated by weighted random vectors can be reduced to short sequences with less computation time.     

Adaptive control of surviving symbol replica candidates in QRM-MLD for OFDM MIMO multiplexing

This paper proposes adaptive control of the number of surviving symbol replica candidates, S/sub m/ (m denotes the stage index), based on the minimum accumulated branch metric of each stage in maximum-likelihood detection employing QR decomposition and the M-algorithm (QRM-MLD) in orthogonal frequency-division multiplexing with multiple-input-multiple-output (MIMO) multiplexing. In the proposed algorithm, S/sub m/ at the mth stage (1/spl les/m/spl les/N/sub t/, N/sub t/ is the number of transmission antenna branches) is independently controlled using the threshold value calculated from the minimum accumulated branch metric at that stage and the estimated noise power. We compared the computational complexity of QRM-MLD employing the proposed algorithm with that of conventional methods at the same average packet error rate assuming the information bit rate of 1.048 Gb/s in a 100-MHz channel bandwidth (i.e., frequency efficiency of approximately 10 bit/s/Hz) using 16QAM modulation and turbo coding with the coding rate of 8/9 in 4-by-4 MIMO multiplexing. Computer simulation results show that the average computational complexity of the branch metrics, i.e., squared Euclidian distances, of the proposed adaptive independent S/sub m/ control method is decreased to approximately 38% that of the conventional adaptive common S/sub m/ control and to approximately 30% that of the fixed S/sub m/ method (S/sub m/=M=16), assuming fair conditions such that the maximum number of surviving symbol replicas at each stage is set to M/spl circ/=16.     

Simplicity

Before computing became a way of life, our lives were simpler. There were fewer messages to process on a daily basis, and we generally spent more time on fewer tasks. In that sense, we were a highly unproductive society. Fortunately, we now have modern computing technology, with all its labour-saving capabilities, which allows us to spend minimal amounts of time on an increasing number of tasks. One could consider this the ultimate progression toward the ideal state of productivity — our per-task time is approaching zero, allowing us to, in theory, perform a seemingly infinite number of tasks. Yet we have to question whether these advances are leading to a more satisfying existence. Do we not ache inside for something ... simpler?     

Ultra-thin high-density LSI packaging substrate for advanced CSPs and SiPs

An ultra-thin high-density LSI packaging substrate, called multi-layer thin substrate (MLTS), is described. It meets the demand for chip scale packages (CSPs) and systems in a package (SiPs) for use in recently developed small portable applications with multiple functions. A high-density build-up structure is fabricated on a Cu plate, which is then removed, leaving only an ultra-thin, high-density multi-layer substrate. MLTS has (1) excellent registration accuracy, which enables higher density and finer pitch patterning due to the use of a rigid, excellent-flatness Cu base plate; (2) a thinner multi-layer structure due to the use of a core-less multi-layer structure; (3) excellent reliability, supported by the use of an aramid-reinforced epoxy resin dielectric layer; and (4) a cost-effective design due to the use of fewer layers fabricated using a conventional build-up process. A prototype high-density CSP (0.4-mm pitch/288 pins/4 rows/10 mm²) was fabricated using a 90-μm-thick MLTS (with a solder resist layer). Testing demonstrated that it had excellent long-term reliability. A prototype ultra-thin, high-density SiP (0.5-mm pitch/225 pins/11 mm²/0.93 mm thick) was also fabricated based on MLTS. MLTS consists of only two conductor layers (total thickness: 90 μm) while an identical-function build-up printed wiring board needs four conductor layers (total thickness: 300 μm). With its thinner core-less multi-layer structure, MLTS enables the fabrication of ultra-thin, high-density SiPs.     

A highly integrated 40-MIPS (peak) 64-b RISC microprocessor

A 1-million transistor 64-b microprocessor has been fabricated using 0.8-μm double-metal CMOS technology. A 40-MIPS (million instructions per second) and 20-MFLOPS (million floating-point operations per second) peak performance at 40 MHz is realized by a self-clocked register file and two translation lookaside buffers (TLBs) with word-line transition detection circuits. The processor contains an integer unit based on the SPARC (scalable processor architecture) RISC (reduced instruction set computer) architecture, a floating-point unit (FPU) which executes IEEE-754 single- and double-precision floating-point operations a 6-KB three-way set-associative physical instruction cache, a 2-KB two-way set-associative physical data cache, a memory management unit that has two TLBs, and a bus control unit with an ECC (error-correcting code) circuit     

Wideband and high-gain negative-feedback AGC amplifier for high-speed lightwave digital transmission systems

A negative-feedback AGC amplifier based on a new circuit configuration concept is proposed and monolithically integrated. The amplifier exhibits characteristics 2.5 times superior to those of the conventional AGC amplifier: 410 MHz bandwidth, 16 dB maximum gain and 18 dB gain dynamic range.     

New monolithic AGC amplifier stabilising output DC level for 560 Mbit/s optical transmission

A new AGC amplifier stabilising the output DC level is proposed and monolithically integrated using 1 ?m Si-bipolar IC technology. First, it is proven that the proposed AGC amplifier is about ten times superior to the conventional one in regard of output DC level stability. Next, it is confirmed that the IC, which exhibits a 720 MHz bandwidth, 39 dB maximum gain and 60 dB gain dynamic range, is feasible for 560 Mbit/s optical transmission.