Early detection of heart diseases using a low-cost compact ECG sensor

Multimedia Tools and Applications - Heart disease patients are continuously increasing. The patients face the problem of a delayed diagnosis as the subjects do not undergo routine tests and consult...     

Correction to: EDVWDD: Event‑Driven Virtual Wheel‑based Data Dissemination for Mobile Sink‑Enabled Wireless Sensor Networks

The Journal of Supercomputing - A correction to this paper has been published: https://doi.org/10.1007/s11227-021-03790-9     

Laser micro-welding of aluminum and copper with and without tin foil alloy

In this paper continuous laser welding of two dissimilar materials, aluminum and copper, was investigated. The aluminum and the copper utilized were Al3003-H14 and Cu110-H00, respectively. Two different sets of samples were laser welded; one in which a filler material, tin foil alloy (S-bond 220), was sandwiched between the aluminum and the copper and another set in which the aluminum and copper were directly welded without any filler. The foil alloy was utilized to enhance the compatibility of the two metals; aluminum and copper, reducing the brittleness of the intermetallic compound that may form and, subsequently, enhance the mechanical properties. The welding was carried out using an IPG 500 SM fiber laser. The length of the laser joint produced was 20 mm and the width was about 200 μm. The strength of the joint was evaluated by conducting the lap shear stress test. Samples in which filler foil was used exhibited a better performance in the lap shear stress test (an average of 780 N) than the samples without tin foil (an average of 650 N). The improvement in the lap shear test could be attributed to the positive effects of the filler on enhancing the compatibility of the intermetallic compound formed via diffusion. The fracture surface of both types of joints (with and without filler) was characterized using scanning electron microscope equipped with energy-dispersive X-ray (EDAX). To understand the failure initiation and propagation of the samples under tension, a finite element (FE) model was developed for the samples created with no filler material. The failure mechanism predicted from the FE model matches reasonably well with the experimental observations from EDAX analysis.     

Compiler-assisted energy optimization for clustered VLIW processors

Clustered architecture processors are preferred for embedded systems because centralized register file architectures scale poorly in terms of clock rate, chip area, and power consumption. Although clustering helps by improving the clock speed, reducing the energy consumption of the logic, and making the design simpler, it introduces extra overheads by way of inter-cluster communication. This communication happens over long global wires having high load capacitance which leads to delay in execution and significantly high energy consumption. Inter-cluster communication also introduces many short idle cycles, thereby significantly increasing the overall leakage energy consumption in the functional units. The trend towards miniaturization of devices (and associated reduction in threshold voltage) makes energy consumption in interconnects and functional units even worse, and limits the usability of clustered architectures in smaller technologies. However, technological advancements now permit the design of interconnects and functional units with varying performance and power modes. In this paper, we propose scheduling algorithms that aggregate the scheduling slack of instructions and communication slack of data values to exploit the low-power modes of functional units and interconnects. Finally, we present a synergistic combination of these algorithms that simultaneously saves energy in functional units and interconnects to improves the usability of clustered architectures by achieving better overall energy–performance trade-offs. Even with conservative estimates of the contribution of the functional units and interconnects to the overall processor energy consumption, the proposed combined scheme obtains on average 8% and 10% improvement in overall energy–delay product with 3.5% and 2% performance degradation for a 2-clustered and a 4-clustered machine, respectively. We present a detailed experimental evaluation of the proposed schemes. Our test bed uses the Trimaran compiler infrastructure.     

On the sizing of a solar thermal electricity plant for multiple objectives using evolutionary optimization

Design, implementation and operation of solar thermal electricity plants are no more an academic task, rather they have become a necessity. In this paper, we work with power industries to formulate a multi-objective optimization model and attempt to solve the resulting problem using classical as well as evolutionary optimization techniques. On a set of four objectives having complex trade-offs, our proposed procedure first finds a set of trade-off solutions showing the entire range of optimal solutions. Thereafter, the evolutionary optimization procedure is combined with a multiple criterion decision making (MCDM) approach to focus on preferred regions of the trade-off frontier. Obtained solutions are compared with a classical generating method. Eventually, a decision-maker is involved in the process and a single preferred solution is obtained in a systematic manner. Starting with generating a wide spectrum of trade-off solutions to have a global understanding of feasible solutions, then concentrating on specific preferred regions for having a more detailed understanding of preferred solutions, and then zeroing on a single preferred solution with the help of a decision-maker demonstrates the use of multi-objective optimization and decision making methodologies in practice. As a by-product, useful properties among decision variables that are common to the obtained solutions are gathered as vital knowledge for the problem. The procedures used in this paper are ready to be used to other similar real-world problem solving tasks.     

Compiler-assisted power optimization for clustered VLIW architectures

Clustered VLIW architectures solve the scalability problem associated with flat VLIW architectures by partitioning the register file and connecting only a subset of the functional units to a register file. However, inter-cluster communication in clustered architectures leads to increased leakage in functional components and a high number of register accesses. In this paper, we propose compiler scheduling algorithms targeting two previously ignored power-hungry components in clustered VLIW architectures, viz., instruction decoder and register file.We consider a split decoder design and propose a new energy-aware instruction scheduling algorithm that provides 14.5% and 17.3% benefit in the decoder power consumption on an average over a purely hardware based scheme in the context of 2-clustered and 4-clustered VLIW machines. In the case of register files, we propose two new scheduling algorithms that exploit limited register snooping capability to reduce extra register file accesses. The proposed algorithms reduce register file power consumption on an average by 6.85% and 11.90% (10.39% and 17.78%), respectively, along with performance improvement of 4.81% and 5.34% (9.39% and 11.16%) over a traditional greedy algorithm for 2-clustered (4-clustered) VLIW machine.     

A three-axis SOI accelerometer sensing with both in-plane and vertical comb electrodes

A three-axis capacitive accelerometer based on silicon-on-insulator is designed and fabricated. In the accelerometer, totally eight groups of capacitors are compactly arranged around an octagonal proof mass. The four groups of capacitors along orthogonal direction with in-plane comb electrodes detect XY acceleration, while the other four groups of capacitors along diagonal direction with vertical comb electrodes detect Z acceleration. Measurements of in-plane and vertical motion by the respective in-plane and vertical comb electrodes enable direct detection for all the three axes with differential capacitive sensing scheme. For the fabricated accelerometer in the size of 4 × 4 mm², the capacitance sensitivities of in-plane and out-of-plane accelerometers are 145.3 and 9.1 fF/g, respectively.     

Load Balancing Parallel Explicit State Model Checking

This paper first identifies some of the key concerns about the techniques and algorithms developed for parallel model checking; specifically, the inherent problem with load balancing and large queue sizes resultant in a static partition algorithm. This paper then presents a load balancing algorithm to improve the run time performance in distributed model checking, reduce maximum queue size, and reduce the number of states expanded before error discovery. The load balancing algorithm is based on generalized dimension exchange (GDE). This paper presents an empirical analysis of the GDE based load balancing algorithm on three different supercomputing architectures—distributed memory clusters, Networks of Workstations (NOW) and shared memory machines. The analysis shows increased speedup, lower maximum queue sizes and fewer total states explored before error discovery on each of the architectures. Finally, this paper presents a study of the communication overhead incurred by using the load balancing algorithm, which although significant, does not offset performance gains.     

Scalable hybrid computation with spikes

We outline a hybrid analog-digital scheme for computing with three important features that enable it to scale to systems of large complexity: First, like digital computation, which uses several one-bit precise logical units to collectively compute a precise answer to a computation, the hybrid scheme uses several moderate-precision analog units to collectively compute a precise answer to a computation. Second, frequent discrete signal restoration of the analog information prevents analog noise and offset from degrading the computation. And, third, a state machine enables complex computations to be created using a sequence of elementary computations. A natural choice for implementing this hybrid scheme is one based on spikes because spike-count codes are digital, while spike-time codes are analog. We illustrate how spikes afford easy ways to implement all three components of scalable hybrid computation. First, as an important example of distributed analog computation, we show how spikes can create a distributed modular representation of an analog number by implementing digital carry interactions between spiking analog neurons. Second, we show how signal restoration may be performed by recursive spike-count quantization of spike-time codes. And, third, we use spikes from an analog dynamical system to trigger state transitions in a digital dynamical system, which reconfigures the analog dynamical system using a binary control vector; such feedback interactions between analog and digital dynamical systems create a hybrid state machine (HSM). The HSM extends and expands the concept of a digital finite-state-machine to the hybrid domain. We present experimental data from a two-neuron HSM on a chip that implements error-correcting analog-to-digital conversion with the concurrent use of spike-time and spike-count codes. We also present experimental data from silicon circuits that implement HSM-based pattern recognition using spike-time synchrony. We outline how HSMs may be used to perform learning, vector quantization, spike pattern recognition and generation, and how they may be reconfigured.