Application of Support Vector Machines in Assessing Conceptual Cost Estimates

Total conceptual cost estimates and the assessment of the quality of these estimates are critical in the early stages of a building construction project. In this study, the support vector machine (SVM) model for assessing the quality of conceptual cost estimates is proposed, and the application of SVM in construction areas is investigated. The results show that the SVM model assessed the quality of conceptual cost estimates slightly more accurately than the discriminant analysis model. This shows that using the SVM has potential in construction areas. In addition, the SVM model can assist clients in their evaluation of the quality of the estimated cost and the probability of exceeding the target cost, and in their decision on whether or not it is necessary to seek a more accurate estimate in the early stages of a project.     

钛合金植入物材料的表面改性研究进展

简介了钛合金植入物材料的开发及表面改性技术。     

Structuring communication software for quality-of-serviceguarantees

We propose architectural mechanisms for structuring host communication software to provide QoS guarantees. We present and evaluate a QoS sensitive communication subsystem architecture for end hosts that provides real time communication support for generic network hardware. This architecture provides services for managing communication resources for guaranteed QoS (real time) connections, such as admission control, traffic enforcement, buffer management, and CPU and link scheduling. The architecture design is based on three key goals: maintenance of QoS guarantees on a per connection basis, overload protection between established connections, and fairness in delivered performance to best effort traffic. Using this architecture we implement real time channels, a paradigm for real time communication services in packet switched networks. The proposed architecture features a process per channel model that associates a channel handler with each established channel. The model employed for handler execution is one of “cooperative” preemption, where an executing handler yields the CPU to a waiting higher priority handler at well defined preemption points. The architecture provides several configurable policies for protocol processing and overload protection. We present extensions to the admission control procedure for real time channels to account for cooperative preemption and overlap between protocol processing and link transmission at a sending host. We evaluate the implementation to demonstrate the efficacy with which the architecture maintains QoS guarantees on outgoing traffic while adhering to the stated design goals     

试论双点后方交会简便公式

根据双点后方交会的图形特点和已知条件，列出了方程组，推导出了双点后方交会直接计算座标的简便公式，同时求出了精度计算公式，以供测量人员参考     

An effective rhodium catalyst system on the synthesis of acetic acid from methyl formate

Rh/Lil/SnR₄ is an effective catalyst system for the conversion of methyl formate to acetic acid under carbon monoxide pressure. The effects of solvent and initial CO partial pressure on the turnover rate of the reaction were investigated. The possibility of replacing some of the iodide promoters by tin compounds has been probed.     

HYDRODYNAMIC FORCE ON SMOOTH HORIZONTAL CYLINDER IN UNIFORM OSCILLATORY FLOW

ＨＹＤＲＯＤＹＮＡＭＩＣ　ＦＯＲＣＥ　ＯＮ　ＳＭＯＯＴＨ　ＨＯＲＩＺＯＮＴＡＬ　ＣＹＬＩＮＤＥＲ　ＩＮ　ＵＮＩＦＯＲＭ　ＯＳＣＩＬＬＡＴＯＲＹ　ＦＬＯＷＨＹＤＲＯＤＹＮＡＭＩＣＦＯＲＣＥＯＮＳＭＯＯＴＨＨＯＲＩＺＯＮＴＡＬＣＹＬＩＮＤＥＲＩＮＵＮＩＦ...     

Room temperature characterization of Hg1-xCdxTe P-on-n heterostructure photodiodes

Measurements of 77K R_oA and 300K reverse bias dynamic impedance (R_dA) products at one volt reverse bias has been carried out to assess the degree of correlation of this figure of merit. Planar P-on-n heterostructures were grown on near lattice-matched CdZnTe substrates with Hg_1-xCd_xTe (0.20< x <0.30) by molecular beam epitaxy. These devices were passivated with CdTe and doped with indium and arsenic as n- and p-type dopants, respectively. Current-voltage characteristic of these devices exhibit thermally generated dark currents at small and modest reverse bias. We have observed that R_oA values of these long wavelength infrared P-on-n heterostructure photodiodes at 77K correlate with room temperature R_dA values. Diode arrays with high room temperature R_dA values at one volt reverse bias also have high R_oA values at 77K. Similarly, low R_dA values at room temperature indicate poor performance at 77K where deviation from diffusion current occurs at reverse bias of 0.2 to 1 volt at room temperature. The results presented here, for a small samples of devices, demonstrate that room temperature measurements of current-voltage characteristics to evaluate Hg_1-xCd_xTe (0.22< x <0.28) diode performance and array uniformity at lower temperatures can be used. This provides an acceptable criteria for further study at lower temperatures.     

1.04 GBd low EMI digital video interface system using small swingserial link technique

In a high-resolution flat panel system, a conventional interface that directly connects a liquid crystal display (LCD) controller to a flat panel cannot overcome the problems of excess EMI (electromagnetic interference) and power caused by full-swing transmission signals in parallel lines. This paper presents a high-speed digital video interface system implemented with a low-cost standard CMOS (complimentary metal-oxide-semiconductor) technology that can mitigate EMI and power problems in high-resolution flat panel display systems. The combined architecture of the high-speed, small number of parallel lines and low-voltage swing serial interface can support resolutions from VGA (640×480 pixels) up to XGA (1024×768 pixels) with significant power improvement and drastic EMI reduction. To support high-speed, low-voltage swing signaling and overcome channel-to-channel skew problems, a robust data recovery system is required. The proposed digital phase-locked loop enables robust skew-insensitive data recovery of up to 1.04 GBd     

Peptide YY inhibition of rat gastric enterochromaffin-like cell function

The present study determined tumorigenicity, tumor classification and DNA damage induced in infant mice by benzo[a]pyrene (B[a]P) or Manufactured Gas Plant (MGP) residues after a single exposure. Male and female B6C3F1 mice were exposed to B[a]P or MGP residue from a single environmental site (MGP-4) and males were also exposed to MGP residue composite from seven different sites (MGP-M7). At 26, 39 and 52 weeks after exposure tumorigenesis was assessed in lung, forestomach and liver. Formation and persistence of DNA adducts were quantified by 32P-postlabeling. Exposure of males to B[a]P induced liver tumors in a dose and time dependent manner. MGP induced more advanced tumors than B[a]P. Only a single liver tumor was found in MGP-4 treated females. No forestomach and few pulmonary adenomas were induced in males or females. MGP-4, MGP-M7 or B[a]P induced DNA adducts in males and females. Adducts in liver, lung and forestomach peaked on different days and decreased at different rates. At 24 h post-exposure, no significant differences in initial DNA adduct levels occurred in males and females exposed to MGP-4 or B[a]P. Lack of DNA damage (adducted DNA) did not account for non-responsiveness of lung and forestomach in B6C3F1 genders as well as in liver in females. MGP tumorigenicity could not be accounted for solely by B[a]P content nor did it reflect additivity of B[a]P and other carcinogenic polycyclic aromatic hydrocarbons (PAHs) in MGP. Synergy among MGP-PAHs, presence of unidentified carcinogens and/or promoters in MGP may account for MGP potency. The B6C3F1 infant male model is a convenient and rapid assay for assessing MGP liver tumorigenicity and potency.     

A 200-MHz complex number multiplier using redundant binaryarithmetic

Modern digital communication systems rely heavily on baseband signal processing for in-phase and quadrature (I-Q) channels, and complex number processing in low-voltage CMOS has become a necessity for channel equalization, timing recovery, modulation, and demodulation. In this work, redundant binary (RB) arithmetic is applied to complex number multiplication for the first time so that an N-bit parallel complex number multiplier can be reduced to two RE multiplications (i.e., an addition of N RB partial products) corresponding to real and imaginary parts, respectively. This efficient RE encoding scheme proposed can generate RB partial products with no additional hardware and delay overheads. A prototype 8-bit complex number multiplier containing 11.5 K transistors is integrated on 1.05×1.33 mm² using 0.8 μm CMOS. The chip consumes 90 mW with 2.5 V supply when clocked at 200 MHz