1.5%-/spl Delta/ athermal arrayed-waveguide grating multi/demultiplexer with very low loss groove design

We describe a compact 1.5%-/spl Delta/ athermal silica-based 100-GHz-spacing 16-channel arrayed-waveguide grating (AWG) multi/demultiplexer with a modified groove design for a very low excess loss. We propose new approaches for modifying the shape of the grooves and the arrayed waveguides and optimize the shape modifications for 1.5%-/spl Delta/ waveguides. By employing this modified groove design, we greatly reduced the groove excess loss from 1.9 to 0.4 dB in the 1.5%-/spl Delta/ athermal AWG.     

Low-loss athermal silica-based lattice-form interleave filter with silicone-filled grooves

We describe a low-loss athermal silica-based interleave filter with a lattice-form structure. We athermalize the filter by using a silicone-filled groove formed in each delay line and we employ a low-loss design to reduce the accumulated groove excess loss in the multiple delay lines. By using these designs, we obtained a very low groove excess loss of 0.4 dB and achieved satisfactory temperature insensitivity and optical characteristics with this filter.     

Extremely low-loss 1.5%-/spl Delta/ 32-channel athermal arrayed-waveguide grating multi/demultiplexer

A silica-based 1.5%-/spl Delta/ 100 GHz-spacing 32-channel athermal arrayed-waveguide grating (AWG) with compact size and extremely low insertion loss is described. By reducing the fibre coupling loss and the excess loss in a silicone-filled groove, an insertion loss of 1.3 dB was achieved with this athermal AWG.     

A delay-encoding-logic array processor for dynamic-programming matching of data sequences

Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.     

Influence of buried structure on polarization sensitivity instrained bulk semiconductor optical amplifiers

In order to achieve an accurate design of polarization-insensitive semiconductor optical amplifiers based on tensile strained bulk InGaAsP, the reduction of strain in the active layer of the buried heterostructure and its influence on polarization sensitivity are analyzed numerically for the first time. The gain calculation, including the strain distribution in the active layer, is examined based on the k · p method for the different active layers. It is found that the strain introduced during the epitaxial growth is strongly reduced after regrowth of the burying layer. In an active layer having the aspect ratio of 1 : 4, the strain reduction causes more than a 0.5-dB deviation in the polarization sensitivity of the gain. From a comparison with the experimental results, it is shown that including the effect of the burying layer in the calculation gives an accurate determination of the amount of strain for the polarization independence     

1-GHz-spaced 16-channel arrayed-waveguide grating for a wavelength reference standard in DWDM network systems

We fabricated a 1-GHz-spaced 16-channel arrayed-waveguide grating (AWG) by using a new AWG configuration where the path of each arrayed waveguide winds backward and forward across a 4-in diameter wafer without crossing any other waveguides. The ultra-narrow (< 1 GHz) and stable transmission bands of this AWG can be used to construct a wavelength reference standard covering the S, C, and L bands in the dense wavelength-division-multiplexing network systems whose frequency deviation is /spl plusmn/160 MHz.     

High performance 35 nm gate length CMOS with NO oxynitride gate dielectric and Ni salicide

The 35 nm gate length CMOS devices with oxynitride gate dielectric and Ni salicide have been fabricated to study the feasibility of higher performance operation. Nitrogen concentration in gate oxynitride was optimized to reduce gate current I/sub g/ and to prevent boron penetration in the pFET. The thermal budget in the middle of the line (MOL) process was reduced enough to realize shallower junction depth in the S/D extension regions and to suppress gate poly-Si depletion. Finally, the current drives of 676 /spl mu/A//spl mu/m in nFET and 272 /spl mu/A//spl mu/m in pFET at V/sub dd/=0.85 V (at I/sub off/=100 nA//spl mu/m) were achieved and they are the best values for 35 nm gate length CMOS reported to date.     

适于运动估值VLSI实现的改进的树结构

文中给出了一种用于实现多分辨率运动估算算法后阶段任务的改进的树结构。在一个简单的RISC类型核控制下,它能够完成整个运动估值过程中除粗分辨率精度运动矢量搜索之外的所有后阶段子任务。包括运动矢量优化（搜索）在内的多任务是通过二叉树最底层叶节点上的多功能处理单元和可以拆分成子树的加法树来实现的。此外,运算单元寄存器堆的设计使能在二维方向上复用图像数据,完全避免了同一类数据从存储器中重复读取,从而实现了最小的存储器访问带宽,并有助于减小存储功耗。     

10-GHz-spaced 1010-channel tandem AWG filter consisting of oneprimary and ten secondary AWGs

A very large channel-count arrayed waveguide grating (AWG) filter with more than 1000 channels is described. It was achieved by cascading a 1-THz-spaced flat-top 1×10 AWG as a primary filter and ten 10-GHz-spaced 1×160 AWGs as secondary filters in a tandem configuration. We achieved good adjacent and accumulated channel crosstalk values ranging from -32 to -25 dB and from -24 and -18 dB, respectively     

A real-time motion estimation and compensation LSI with wide searchrange for MPEG2 video encoding

This paper presents a motion estimation and compensation large scale integration (LSI) for the MPEG2 standard. An embedded RISC processor and special hardware modules enable the LSI to achieve a sufficient ability to perform real-time operation and provide the availability to realize many kinds of block matching algorithms. Using a three-step hierarchical telescopic search algorithm, a single chip accomplishes real-time motion estimation with search ranges of ±32.5×±32.5 pixels for motion vectors. The chip was fabricated using 0.5-μm CMOS technology and has an area of 16.5×16.5 mm² and 2.0 M transistors