Investigation of Gold Nanoparticle Inks for Low-Temperature Lead-Free Packaging Technology

Gold nanoparticle inks were investigated as a potential candidate for lead-free packaging applications. Inks consisted of surfactant-passivated nanoparticles dissolved in a solvent. Optimized gold inks are able to sinter at temperatures as low as 120°C and achieve conductivities of up to 70% of bulk. Once sintered, the metallic structure reverts to bulk-like properties and approaches bulk reliability and performance. Thus nanoparticle-based solders would operate at much lower homologous temperatures as compared with alloy-based solders. Nanoparticle inks under investigation were sintered at 180°C. The resulting material exhibited a resistivity of 5 μΩ cm, which is significantly lower than those of Pb-Sn and Sn-Ag-Cu. Electromigration studies were carried out and time to failure was investigated as a function of temperature. Electromigration activation energy was calculated through Black’s equation to be 0.52 eV, which is consistent with surface/grain boundary diffusion. These studies suggest that nanoparticle-ink-based films show excellent robustness, due to their irreversible conversion to bulk-like materials. Nanoparticle inks are thus promising candidates for next-generation lead-free solders.     

Reliability of Au-Ge and Au-Si Eutectic Solder Alloys for High-Temperature Electronics

High-temperature electronics will facilitate deeper drilling, accessing harder-to-reach fossil fuels in oil and gas industry. A key requirement is reliability under harsh conditions for a minimum continuous operating time of 500?h at 300°C. Eutectic solder alloys are generally favored due to their excellent fatigue resistance. Performance of Au-Ge and Au-Si eutectic solder alloys at 300°C up to 500?h has been evaluated. Nanoindentation results confirm the loss of strength of Au-Ge and Au-Si eutectic solder alloys during thermal aging at 300°C, as a result of grain coarsening. However, the pace at which the Au-Ge eutectic alloy loses its strength is much slower when compared with Au-Si eutectic alloy. The interfacial reactions between these eutectic solder alloys and the underbump metallization (UBM), i.e., electroless nickel immersion gold (ENIG) UBM and Cu/Au UBM, have been extensively studied. Spalling of Au₃Cu intermetallic compound is observed at the interface between Au-Ge eutectic solder and the Cu/Au UBM, when aged at 300°C for 500?h, while the consumption of ENIG UBM is nominal. Unlike the Au-Si solder joint, hot ball shear testing at high temperature confirmed that the Au-Ge joint on ENIG UBM, when aged at 300°C for 500?h, could still comply with the minimum qualifying bump shear strength based on the UBM dimension used in this work. Thus, it has been determined that, among these two binary eutectic alloys, Au-Ge eutectic alloy could fulfill the minimum requirement specified by the oil and gas exploration industry.     

Comparative performance of some polynomial-based lowpass filters for microwave/digital transmission applications

This paper reports on the comparative performances of some polynomial based lowpass filters in the lumped elements, microstrip and defected ground structure (DGS) environment. The microwave designers are normally familiar with Butterworth, Chebyshev and Bessel filters. However, many more polynomials based, ripple and non-ripple types LPF have been suggested for the low-frequency applications. Some of these LPF, such as L-opt, H-type, Transitional Butterworth-Legendre (TBL), Pascal, Legendre group of LPF, are compared for their applications in analog microwaves, digital transmission, efficiency enhancement of the linear power amplifiers and five level partial response modulations. A method is reported to compute the ripple frequency for the Legendre group of LPF and Pascal LPF. Further, a design is suggested to significantly improve group delay performance of high selectivity filters.     

Routing Protocols in Delay Tolerant Networks: Comparative and Empirical Analysis

Wireless Personal Communications - A Delay Tolerant Network (DTN) is a network capable of handling long delays and data loss efficiently in various challenged scenarios and environments. Owing to...     

Smart City Healthcare Cyber Physical System: Characteristics,Technologies and Challenges

Wireless Personal Communications - The recent pandemic has demanded a strong and smart healthcare system which can monitor the patients efficiently and handle the situation that arises from the...     

Channel capacity with suboptimal adaptation technique over generalized-K fading using marginal moment generating function

In this paper we have computed the channel capacity for suboptimal adaptation technique over the generalized-K fading environment. The analytical expression for channel capacity in case of the truncated channel inversion with fixed rate (C_TCIFR) has been exploited in terms of marginal moment generating function (MMGF) and its performance is evaluated over the generalized-K faded environment. The MMGF based approach for the computation of channel capacity has been validated with the reported literature for channel capacity in case of the channel inversion with fixed rate using the suboptimal adaptive technique.     

A low-power up-conversion CMOS mixer for 22-29-GHz ultra-wideband applications

A double-balanced, low-power, and low-voltage dual-gate up-conversion mixer working at K-band is designed and fabricated in the UMC 130-nm logic CMOS process. The mixer achieves a 3-dB conversion-gain bandwidth of 1.8 GHz at the input IF port and a 3-dB conversion-gain bandwidth of 10 GHz at the output RF port. The mixer achieves an output referred 1-dB compression point as high as -5.8 dBm and an output referred third-order intercept point as high as 5.8 dBm, while consuming 8.0 mW from a 1.2-V supply. This study demonstrates that the implementation of low-power mixers operating in the 22-29-GHz band for ultra-wideband automotive radar applications is possible in low-cost and low-voltage logic CMOS technology.     

Comprehensive review for energy efficient hierarchical routing protocols on wireless sensor networks

Wireless Networks - In recent years, wireless sensor networks (WSNs) have played a major role in applications such as tracking and monitoring in remote environments. Designing energy efficient...     

Enhanced ground bounce noise reduction in a low-leakage CMOS multiplier

In this paper, various parameters are used to reduce leakage power, leakage current and noise margin of circuits to enhance their performance. A multiplier is proposed with low-leakage current and low ground bounce noise for the microprocessor, digital signal processors (DSP) and graphics engines. The ground bounce noise problem appears when a conventional power-gating circuit transits from sleep-to-active mode. This paper discusses a reduction in leakage current in the stacking power-gating technique by three modes – sleep, active and sleep-to-active. The simulation results are performed on a 4 × 4 carry-save multiplier for leakage current, active power, leakage power and ground bounce noise, and comparison made for different nanoscales. Ground bounce noise is limited to 90%. The leakage current of the circuit is decimated up to 80% and the active power is reduced to 31%. We performed simulations using cadence virtuoso 180 and 45 nm at room temperature at various supply voltages.