电信级以太环网若干问题探讨

本文对电信级以太环网技术中几个比较重要的问题做了简要的介绍,使读者对电信级以太环网技术有比较全面的了解.     

高速光接收组件同轴结构封装关键技术研究

在接入网中,低成本、小尺寸的同轴结构封装10 Gb/s光接收组件起着非常重要的作用。在微波频段,封装器件引入的寄生参数已经成为制约其高频特性的主要因素之一。基于传输线理论,建立了包含芯片、金丝、管座的小信号等效电路模型。等效电路元件与实际封装器件有对应的关系。组件高频特性随元件参数值变化而变化。仿真结果表明金丝对其高频特性影响很严重。为了减小金丝电感,提出一种优化方案。并结合实际工艺条件,制作了样品,实验结果表明该样品的传输速率达到10 Gb/s,满足10 Gb/s光网络传输的要求。     

A unifying proof of global asymptotical stability of neural networks with delay

We present some new global stability results of neural networks with delay and show that these results generalize recently published stability results. In particular, several different stability conditions in the literature which were proved using different Lyapunov functionals are generalized and unified by proving them using the same Lyapunov functional. We also show that under certain conditions, reversing the directions of the coupling between neurons preserves the global asymptotical stability of the neural network.     

Characteristics and optimization of 4H-SiC MESFET with a novel p-type spacer layer incorporated with a field-plate structure based on improved trap models

A novel structure of 4H-SiC MESFETs is proposed that focuses on surface trap suppression.Characteristics of the device have been investigated based on physical models for material properties and improved trap models.By comparing with the performance of the well-utilized buried-gate incorporated with a field-plate （BG-FP） structure,it is shown that the proposed structure improves device properties in comprehensive aspects. A p-type spacer layer introduced in the channel layer suppresses the surface trap effect and reduces the gate-drain capacitance(C_gd) under a large drain voltage.A p-type spacer layer incorporated with a field-plate improves the electric field distribution on the gate edge while the spacer layer induces less C_gd than a conventional FP.For microwave applications,4H-SiC MESFET for the proposed structure has a larger gate-lag ratio in the saturation region due to better surface trap isolation from the conductive channel.For high power applications,the proposed structure is able to endure higher operating voltage as well.The maximum saturation current density of 460 mA/mm is yielded.Also,the gate-lag ratio under a drain voltage of 20 V is close to 90%.In addition,5%and 17.8%improvements in f_T and f_max are obtained compared with a BG-FP MESFET in AC simulation,respectively.Parameters and dimensions of the proposed structure are optimized to make the best of the device for microwave applications and to provide a reference for device design.     

Imaging‐Guided Combined Photothermal and Radiotherapy to Treat Subcutaneous and Metastatic Tumors Using Iodine‐131‐Doped Copper Sulfide Nanoparticles

Combining different therapeutic strategies to treat cancer by overcoming limitations of conventional cancer therapies has shown great promise in both fundamental and clinical studies. Herein, by adding ¹³¹I when making iodine‐doped CuS nanoparticles, CuS/[¹³¹I]I nanoparticles are obtained, which after functionalization with polyethylene glycol (PEG) are used for radiotherapy (RT) and photothermal therapy (PTT), by utilizing their intrinsic high near‐infrared absorbance and the doped ¹³¹I‐radioactivity, respectively. The combined RT and PTT based on CuS/[¹³¹I]I‐PEG is then conducted, achieving remarkable synergistic therapeutic effects as demonstrated in the treatment of subcutaneous tumors. In the meanwhile, as revealed by bimodal nuclear imaging and computed tomography (CT) imaging, it is found that CuS/[¹³¹I]I‐PEG nanoparticles after being injected into primary solid tumors could migrate to and retain in their nearby sentinel lymph nodes. Importantly, the combined RT and PTT applied on those lymph nodes to assist surgical resection of primary tumors results in remarkably inhibited cancer metastasis and greatly prolonged animal survival. In vivo toxicology studies further reveal that our CuS/I‐PEG is not obviously toxic to animals at fourfold of the treatment dose. This work thus demonstrates the potential of combining RT and PTT using a single nanoagent for imaging‐guided treatment of metastatic tumors.     

An efficient cooperative hybrid routing protocol for hybrid wireless mesh networks

Hybrid wireless mesh networks are the most generic types of wireless mesh networks. Unlike static mesh routers, which have multiple radio interfaces and almost no energy constraint, mobile mesh clients are usually equipped with a single radio interface and have energy limitations. A cooperative hybrid routing protocol (CHRP) combining advantages of proactive and reactive routing protocols by letting them work cooperatively is proposed in this paper, which can adapt to features of both routers and clients. In CHRP, in order to make a proper route selection, channel condition, interference and constrained energy of clients are considered in the node-aware routing metric. Besides, a cross-layer approach is used in CHRP. Both gateway and client oriented data flows are considered comprehensively. The simulation results using ns-3 show the advantage of the proposed CHRP in terms of average packet loss rate, average latency, average network throughput, average energy consumption of clients and the minimum residual energy of clients.     

A high EMS daisy-chain SPI interface for battery monitor system

A high EMS current-mode SPI interface for battery monitor IC (BMIC) is presented to form a daisy-chain bus configuration for the cascaded BMICs and the communication between the MCU and master BMIC. Based on analog and digital mixed filtering technique, the proposed daisy-chain can avoid the isolated communication issue in electromagnetic interference environment, and reduce the extensively required I/O ports of MCU, at the same time reduce the system cost. The proposed daisy-chain interface was introduced in a 6-ch battery monitor IC which was fabricated with 0.35 μm 30 V BCD process. The measurement result shows that the presented daisy-chain SPI interface achieves better EMS performance with different EMI injection while just consuming a total operation current up to 1 mA.     

基于全固型掺镱光子带隙光纤的被动锁模全光纤环形孤子激光器

采用全固型掺镱光子带隙光纤(AS-Yb-PBGF)作增益介质并提供反常群速色散(GVD),设计了一种被动锁模全光纤环形孤子激光器。没有使用任何块状色散补偿元件。因此,该激光器腔型结构简单、紧凑、环境稳定性高,更容易实现全光纤结构。脉冲在激光腔内的传输用广义非线性薛定谔方程描述,并采用分步傅里叶方法数值模拟了该激光器的单孤子运转的动力学过程。计算时,将AS-Yb-PBGF的长度选取为0.4m,改变激光腔内单模光纤(SMF)的长度,得出了最佳运转参数:当AS-Yb-PBGF固定为0.4 m时,选择单模光纤等于0.4 m,就可以实现脉冲宽度为244 fs,脉冲能量为14 pJ和时间带宽乘积为0.32,即接近傅里叶变换极限的单孤子运转。     

Feasibility study of the application of voltage contrast to printed circuit board

Voltage contrast (VC) has been a powerful tool for the failure analysis of integrated circuits and multichip module. As the packing density of printed circuit board (PCB) is increasing, conventional failure analysis methods to detect open or short circuit in PCBs are no longer adequate, and voltage contrast method could be a method for this purpose. However, unlike the cases of integrated circuits and multichip module, there are many areas in PCB that will produce serious charging effect when examine under the scanning electron microscope. One of the areas is the presence of solder mask on PCB.This work examines the feasibility of using voltage contrast for PCB failure analysis. Specially designed PCB is used for experimentation, and it is found that positive bias on one track and zero bias on another copper track provide a better image contrast as compared to negative and zero biases on the tracks. Also, the variation of the image contrast with different spacing between inter copper tracks has studied. It is found that the variation depends on the presence of solder mask and its location. The variation can be very different for negative bias case as compared to the positive bias case.Finite element analysis is also performed to explain the experimental observations. All the observations can be well explained by the charging effect of the solder masks. The charging effect of solder mask is indeed very significant in affecting the image contrast, and it could reduce the contrast to almost zero in some cases.     

Fabrication of Superjunction Trench Gate Power MOSFETs Using BSG‐Doped Deep Trench of p‐Pillar

In this paper, we propose a superjunction trench gate MOSFET (SJ TGMOSFET) fabricated through a simple p pillar forming process using deep trench and boron silicate glass doping process technology to reduce the process complexity. Throughout the various boron doping experiments, as well as the process simulations, we optimize the process conditions related with the p pillar depth, lateral boron doping concentration, and diffusion temperature. Compared with a conventional TGMOSFET, the potential of the SJ TGMOSFET is more uniformly distributed and widely spread in the bulk region of the n drift layer due to the trenched p‐pillar. The measured breakdown voltage of the SJ TGMOSFET is at least 28% more than that of a conventional device.